Hi everyone, I am trying to harden my design and running into some issues I hope i can get clarified. First off the macro I am trying to harden has an absolute size of 300 by 120. When I try to harden the macro I get a warning that it is too small for the power grid settings and thus the grid is scaled. This leads to the macro not fitting neatly into the wrappers PDN which eventually leads to me getting an LVS error where the power network is disconnected. I'm new-ish to asic design, but there are 2 solutions I came up with. The first one would be to reduce the amount of power stripes in the macro so that it doesn't scale it, however I have no clue how to do this using openlane 2. The second solution would be to flatten the design and harden it in one go so that there would not be a macro, however when I try this I get an error during synthesis that there are unmapped cells. I've followed every step in the docs, but can't seem to figure it out. I would like to ask if anyone could help me with either of the 2 solutions, or a third one that I haven't thought up of. Thank you in advance

is hard macro die size is fixed or can be increased?

The current size is such that all the logic fits neatly into the macro, increasing it is technically possible but the added area will only consist of filler cells and decap

any specific reason 300x120?

No, it was just tested which size would fit the logic neatly and as seen from some old forum threads people got it working with even smaller macros

Try 250x250

It works, there is a lot of extra empty space, but let's hope we can fill it in the future of the project :)

Check the pdn configuration.

Appreciate the help