Hi. Does openlane use systemverilog

yes. But limitation coming from Yosys synthesis tools. Refer yosys documentation, which are not supported SV features.

OpenLane 2 supports the Synlig SystemVerilog frontend for Yosys if you set

USE_SYNLIG

to

true

. However, it is less battle-tested than the Yosys Verilog frontend.

You can also request a version of Yosys with Verific as the frontend that works very well. It’s called TabbyCAD and you can request it from YosysHQ on their website

Where do you set the synlig to be true?

In your design's

config.json

.

I did that

yes