I have a strange issue with resets when trying to do post-synthesis simulation via openlane using

iverilog

. I have tracked it down what looks like my flip-flops not being reset. The post synthesis netlist

final/nl/main.nl.v

has the following:

sky130_fd_sc_hd__dfrtp_1 _11706_ (.CLK(clknet_leaf_46_clk),
    .D(_01024_),
    .RESET_B(_00095_),
    .Q(\cpu_0.program_counter_0.program_counter_internal_0.state[0] ));

Looking at the signals, the reset being fed to the flip-flop is low which I think should be when reset triggers, yet the output of the flipflop remains high I'm simulating via cocotb so giving the exact iverilog command isn't super easy, but the files I'm simulating are

${BUILD_DIR}/post_synth_nl_sim.v --override-verilog /home/frans/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v --override-verilog /home/frans/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v

iverilog gives some warnings, but none that obviously look like they would be the cause of this. Any ideas how to proceed?