Modini Ayyagari
08/02/2024, 7:47 PMMitch Bailey
08/02/2024, 11:15 PMgds/user_project_wrapper.gds.gz
verilog/rtl/user_defines.v
I think is the minimum. Someone please correct me if I’m wrong.
If you’re working on an opensource design, please include all files necessary to recreate the design: verilog rtl files, openlane/<block>/config.json
and related files, xschem schematics and related files, and the lvs_config.json
file.Modini Ayyagari
08/05/2024, 11:01 PM