Hi guys, I wanted to analyse/understand a design t...
# sky130
k
Hi guys, I wanted to analyse/understand a design that was taped out in one of the MPW shuttles a couple of years ago using the SKY130 PDK. But unfortunately the original author didn't make a schematic in Xschem..... instead I have access to ngspice netlists and layout files in magic....would it be possible to make an Xschem schematic from either of those sets of files to check their design ?
m
@Koustubh there is no way to automatically generate an Xschem “schematic” from ngspice netlists or magic layout files. I think you can read a spice netlist into xschem, but it will only produce a “schematic” with individual instances that have pins named - the placement is not optimized and there are no wires. @Stefan Schippers Is that correct?
l
I didn't use xschem in the begining. Now I use a mixed approach. For example, I have a full extracted netlist of a layout I've made from scratch with Magic, and I use the extracted netlist inside a Xschem schematic, as it were a code. If you want to use a block that you have only its netlist, you can do this way. Make a symbol, as a black box. Xschem just capture what is in the schematic and generate a netlist, after all. You can include the netlist without schematics as a spice directive .include
👍 1
s
@Mitch Bailey yes, you can create a schematic symbol with the I/O pins matching the top signals of the spice netlist and read the netlist as is. It is a sort of "black box" that you can instantiate in a design or in a test bench. Spice netlists usually do not contain information on the direction of subcircuit interface pins, so symbols created automatically from a spice netlist will have all interfaces with direction "inout" (bidirectional). There is no "one for all" conversion script that creates a xschem schematic from a spice netlist, since the various netlist details and circuit types may differ a lot. One example of a conversion from a netlist to a schematic was done (see CREATE A SCHEMATIC FROM A SPICE NETLIST) for a faulty
sky130_fd_sc_hd
buffer (
sky130_fd_sc_hvl__lsbuflv2hv_1
). The result is shown below. A schematic done this way is not much better than a textual spice netlist. The problem is that a spice netlist does not contain any information on the position (in the schematic) of transistors / components, so translation just instantiates objects preserving connectivity by placing net labels on pins (no wires, it will be an entangled unreadable mess).
👍 1
k
@Stefan Schippers I am talking about this MPW project. I tried taking the
pll_full.spice
netlist from
netlists
folder of this project repo and using the
make_sky130_sch_from_spice.awk
script from the repo you have mentioned to generate a schematic for it. I am looking for a schematic since I have the taped out chip with me and I want to identify the pins/ports in the design so I can probe/test them. But when I try to use the
make_sky130_sch_from_spice.awk
I get "`Permission denied`" error and I can't run things as sudo, since my entire setup of tools has been done using the iic-osic docker image. What changes do I need to make to utilise this script? or is there a better way to find the pins of this chip? Any help would be much appreciated.
m
@Koustubh looking at the file, it doesn’t appear to be executable. Try this
Copy code
awk -f make_sky130_sch_from_spice.awk pll_full.spice
s
@Koustubh Don't expect the script to work "push button". Any netlist to be imported requires some tuning and it is extremely difficult to have a general solution to the problem. However I will take a look at the project and see what can be done.
@Koustubh From a preliminary inspection the
pll_full.spice
is a flattened netlist, so there is no more hierarchy. There are no filter, pd, pd_buffered, divider, ... subcircuits. The extracted netist (pll_full.spice) is just a list of interconnected transistors / backannotated parasitic lumped capacitors. Since the hierarchy is lost you can't regenerate a hierarchic schematic from this netlist. May be there is some other doc / file in the project that could be more helpful to create a schematic from this design.
@Koustubh @Mitch Bailey it is possible to create a schematic of this
pll_full.spice
. I did these steps: • remove the
.control
...
.endc
section (these are simulator commands) • remove the
.lib
line (same reason as above) • wrap the whole netlist into a
.subckt pll_full
/
.ends
• Execute the script
./make_sky130_sch_from_spice.awk pll_full.spice
(make the script executable!,
chmod a+x make_sky130_sch_from_spice.awk
) • the
pll_full.sch
schematic is created. See video.
👍 2
r
@Stefan Schippers i have tried using spice file generated from magic i tried to make schematic but it is not having any connections in the file layout was created using rtl
m
@Rafeeq Khan Mohammed So it looks like you 1. created a digital circuit using openlane. 2. extracted the circuit using magic to get a spice netlist with parasitic capacitances 3. read that spice netlist into xschem Is that correct? There is no way that xschem is going to auto place auto connect that spice netlist into something remotely resembling a schematic. There are proprietary tools such as spicevision that can do that, but I don’t know of any open source tools. However, the good news is that for mixed signal design, you should not need to convert the digital design to a xschem schematic. See https://xschem.sourceforge.io/stefan/xschem_man/tutorial_use_existing_subckt.html and/or https://open-source-silicon.slack.com/archives/C016HUV935L/p1712918622170979?thread_ts=1712915355.738759&cid=C016HUV935L
r
@Mitch Bailey Hello, thank you for your time. Above 3 points you mention are correct I have a few questions regarding the symbol creation process. Do I need to use the spice from the magic extraction? Additionally, I would like to perform post-simulation for the digital part. Could you please provide some guidance on how to achieve this? I appreciate your assistance in this matter. Thank you.
m
@Stefan Schippers guide here has everything you need to know, I think. I think there’s a way to use the extracted spice to create a symbol, but it’s not necessary. When you say “post-simulation” do you mean “post-layout simulation”? If so, the instructions are in the guide.
r
@Mitch Bailey thank you so much
👍 1