Got my clear on last Friday, I measure xclk at @10MHz and ~@48MHz at IO36. The management SoC seems to work OK, I played with the PLL and measure the changes on xclk successful, but I were unable to test any example that from the CLEAR git, nor any example of the SOFA branch of the synth tools, nor any simple counter (trying to infer clk auto-magically as stated in the Readme). Does anyone have a minimal example that work on the FPGA side? I configure the FPGA with ftdi_fpga.py, does it have a difference if I program the FPGA with process_bit_stream?

Hi, please see my reply in the previous post.

And my results 🙂

In fact, I thought that and_2 did not work because it took a really long time to get the FPGA programmed (~45 seconds). Luckily, with some adjustments, I got it programmed in ~3 seconds. BTW, what PLL configuration did you use to put it @50MHz? My management SoC stopped working with more than 25MHz.

I didn't do anything special that I'm aware of... I believe the "onboard" FPGA clock is acutally just the caravel management SoC wishbone bus clock just being fed in (running at 5x the caravel system clock); the rest of the wishbone bus lines are not connected to anything internally so there's no actual other contention/purpose for it. There are no hard IP PLL blocks in the FPGA implementation that I'm aware of.

The PLL is in the management SoC, but trying to put over 25MHz don't work for me, below that I can change the clock without problem

I'll have to look through the provided housekeeping subroutines, but my LA is convinced that the FPGA clock is running at 50MHz... maybe some reconfig of the wishbone bus is required.

For the PLL make sure you are using a possible internal frequency range: https://github.com/efabless/caravel/pull/537

I got the FPGA to load in 1.5 seconds through the integrated UART, but the speed limits come on because apparently there is no configurable UART divisor.