For the default "and_gate" example, do we know what voltage logic levels is the eFPGA expecting to receive/send on and gates "in" pins 31 and 32 and "out" pins 33? I'm currently not able to get any correct output after flashing the prebuilt "and_gate.hex" firmware. I do have the 6 fpga/gpio pins shorted together as instructed in the readme.md.

The I/O voltage is 3.3V. But I too have issues with the and_gate example, even after changing it to send the bitstream via

process_bit_stream

.

#include <common.h>
#include <and_2.h>

void main()
{
    int i = 0;

    // FPGA IOs
    configure_gpio(1, GPIO_MODE_USER_STD_INPUT_NOPULL);
    configure_gpio(9, GPIO_MODE_USER_STD_INPUT_NOPULL);
    configure_gpio(23, GPIO_MODE_USER_STD_OUTPUT);
    configure_gpio(29, GPIO_MODE_USER_STD_INPUT_NOPULL);
    configure_gpio(34, GPIO_MODE_USER_STD_INPUT_NOPULL);
    configure_gpio(35, GPIO_MODE_USER_STD_INPUT_NOPULL);
    configure_gpio(37, GPIO_MODE_USER_STD_INPUT_NOPULL);

    // ==
    configure_gpio(24, GPIO_MODE_MGMT_STD_OUTPUT); // connected to prog_clk
    configure_gpio(19, GPIO_MODE_MGMT_STD_OUTPUT); // connected to prog_rst
    configure_gpio(18, GPIO_MODE_MGMT_STD_OUTPUT); // connected to op_rst
    configure_gpio(17, GPIO_MODE_MGMT_STD_OUTPUT); // connected to isol_n
    configure_gpio(20, GPIO_MODE_MGMT_STD_OUTPUT); // connected to ccff_head
    configure_gpio(21, GPIO_MODE_MGMT_STD_OUTPUT); // connected to clk_sel

    // and gate
    configure_gpio(31, GPIO_MODE_USER_STD_INPUT_PULLDOWN); // in[121] -> GPIO[31]
    configure_gpio(32, GPIO_MODE_USER_STD_INPUT_PULLDOWN); // in[120] -> GPIO[32]
    configure_gpio(33, GPIO_MODE_USER_STD_OUTPUT); // out[122] -> GPIO[30]

    gpio_config_load();
    process_bit_stream(and_2_size, and_2);

    configure_mgmt_gpio();
    mgmt_gpio_wr(1); // turn on the LED

    while (1){
        mgmt_gpio_wr(i);
        i ^= 1;
    }
}

This code worked for Michael Welling, but not for me. (Note that the third comment on GPIO 33 is wrong.) You can take a look at what we tried so far in this channel: https://discord.gg/AdAXWbvBQQ Btw. the 6 FPGA/GPIO pins are shorted by default on the board.

Thank you @Leo Moser.. had to break out my microscope to see those very well camouflaged traces between the exposed jumper pads.

Great, I'm glad to hear that! (Not so great that it does not work for me 😅️)