<@U016EM8L91B> in my chips i used r1c and via 1 in...
# rerams
samarth jain
07/24/2024, 1:51 PM@Tim Edwards in my chips i used r1c and via 1 instead of r1c and r1v for rram, like this and my rram devices r showing short. is it that my chips dont have rrams? shuttle 2309-R. both via 1 and r1v look same from data sheet from skywater for cadence
t
Tim Edwards
07/24/2024, 1:57 PMThe via1 layer is the same in all cases for the drawn layer; the r1c and r1v layers are never drawn. There is a "reram" layer (GDS layer 68/44) that is used by the foundry to create all of the ReRAM-related masks.
s
samarth jain
07/24/2024, 2:01 PMI am using cadence. skywater only provide r1c and r1v as shown in snip. It’s from their cadence data sheet. this is how I was told by skywater to do the layout but my devices show 1kohms resistance at 0.7v bl voltage @Tim Edwards
t
Tim Edwards
07/24/2024, 3:09 PMIt looks like the Cadence
r1cs
samarth jain
07/24/2024, 3:34 PMSo to confirm, putting extra via like r1v is not needed if I already inserted rram r1c? I will do more measurements tomorrow with ur inputs in mind. Thanks so much. Also how can I get the layer map?
t
Tim Edwards
07/24/2024, 3:37 PMWhat you showed in the screenshot looks correct to me.
r1c / r1vvia1layer.mapd
David Lindley
07/25/2024, 1:04 PM@samarth jain The layermap in V2.1.307 Cadence S130 PDK is in $PDK_HOME/LIBS/S130/S130.layermap. We have code that checks for reram layers in the OAS file and your 2309 submission has the reram layers in it.
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samarth jain
07/26/2024, 8:18 AMWhen I probe bl1 and bl2 after making io8 and io 9 as analog inputs, I get only 5 kohms only when device is prestige. @Tim Edwards @Anton Maurovic (efabless support) @Mitch Bailey.each bl has rram in series. (1t2r) . I made the respective pads as user analog std io in firmware as shown below
samarth jain
07/26/2024, 8:20 AM#include defs.h
#include stub.h
// --------------------------------------------------------
// Firmware routines
// --------------------------------------------------------
void configure_io()
{
// ======= Useful GPIO mode values =============
// GPIO_MODE_MGMT_STD_INPUT_NOPULL
// GPIO_MODE_MGMT_STD_INPUT_PULLDOWN
// GPIO_MODE_MGMT_STD_INPUT_PULLUP
// GPIO_MODE_MGMT_STD_OUTPUT
// GPIO_MODE_MGMT_STD_BIDIRECTIONAL
// GPIO_MODE_MGMT_STD_ANALOG
// GPIO_MODE_USER_STD_INPUT_NOPULL
// GPIO_MODE_USER_STD_INPUT_PULLDOWN
// GPIO_MODE_USER_STD_INPUT_PULLUP
// GPIO_MODE_USER_STD_OUTPUT
// GPIO_MODE_USER_STD_BIDIRECTIONAL
// GPIO_MODE_USER_STD_ANALOG
// ======= set each IO to the desired configuration =============
// GPIO 0 is turned off to prevent toggling the debug pin; For debug, make this an output and
// drive it externally to ground.
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_ANALOG;
// Changing configuration for IO[1-4] will interfere with programming flash. if you change them,
// You may need to hold reset while powering up the board and initiating flash to keep the process
// configuring these IO from their default values.
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
// -------------------------------------------
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // UART Rx
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; // UART Tx
reg_mprj_io_7 = GPIO_MODE_USER_STD_ANALOG; //analog0
reg_mprj_io_8 = GPIO_MODE_USER_STD_ANALOG; //analog1
reg_mprj_io_9 = GPIO_MODE_USER_STD_ANALOG; //analog2
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_USER_STD_ANALOG; //analog6
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
// Initiate the serial transfer to configure IO
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
}
void delay(const int d)
{
/* Configure timer for a single-shot countdown */
reg_timer0_config = 0;
reg_timer0_data = d;
reg_timer0_config = 1;
// Loop, waiting for value to reach zero
reg_timer0_update = 1; // latch current value
while (reg_timer0_value > 0) {
reg_timer0_update = 1;
}
}
void main()
{
int i, j, k;
reg_gpio_mode1 = 1;
reg_gpio_mode0 = 0;
reg_gpio_ien = 1;
reg_gpio_oe = 1;
configure_io();
reg_uart_enable = 1;
// Configure All LA probes as inputs to the cpu
reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
// write data to la output
// reg_la0_data = 0x00;
// reg_la1_data = 0x00;
// reg_la2_data = 0x00;
// reg_la3_data = 0x00;
// read data from la input
// data0 = reg_la0_data;
// data1 = reg_la1_data;
// data2 = reg_la2_data;
// data3 = reg_la3_data;
print("Hello World !!");
while (1) {
reg_gpio_out = 1; // OFF
reg_mprj_datal = 0x00000000;
reg_mprj_datah = 0x00000000;
delay(800000);
// delay(8000000);
reg_gpio_out = 0; // ON
reg_mprj_datah = 0x0000003f;
reg_mprj_datal = 0xffffffff;
delay(800000);
// delay(8000000);
}
}
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