Hello Professor Boris Murmann, may I ask if extracting output driving resistance can be done using no-load delay/(0.69 * Cself load)？

For a logic gate? Note that the calculation finds an equivalent resistance that makes the RC delay model work. The output of a logic gate looks more like a current source that a resistor.

Yes, what I mean is to calculate the equivalent resistance that makes the RC delay model work，Is the above method feasible？

Yes.

Thank you for your answer. I have also read your gm/id book and I have a question. When sizing the transmission gate, the VDS of the transmission gate will change. Would using VDS=0 to search for Ro make the actual Ro greater than the Ro found in the lookup table？

Why would VDS change? Ro is defined for VDS=0.

For example, at the beginning, if the voltage on the capacitor is 0 and VIN is 0.5, the capacitor will be charged to 0.5, and during this process, VDS will change

You are not understanding the approximation being made in switch modeling. The switch is modeled by its small signal equivalent in steady state.

I think the meaning of steady state refers to the Ro during the period when VOUT approaches VIN and VDS is very small？