samarth jain
07/19/2024, 1:47 PMMitch Bailey
07/19/2024, 2:24 PManalog_io[0] = gpio 7
…
analog_io[28] = gpio 35
From caravel_user_project/verilog/rtl/user_project_wrapper.v
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
samarth jain
07/19/2024, 3:24 PMAnton Maurovic (efabless support)
07/19/2024, 3:55 PMreg_la3_data
with the value 0x00000011, which means you're writing LA[127:96] with the pattern: 32'b0000_0000_0*000*_*000*0_0000_0000_0001_0001 -- This is turning on only LA[100] and LA[96], and turning the other 30 bits off.
If you want to hit LA[118:113] then you need to target bit indices 22 down to 17 of the reg_la3_data
register's full 32 bits. For example, writing 0x00560000 (32'b0000_0000_0*101*_*011*0_0000_0000_0000_0000) to this register would set LA[118:113] = 6'b101011. Likewise, maybe line 123 needs to be adjusted for your needs? It is turning on LA[39:36], and turning off the others in the range LA[63:31].
Does that help? The comments on line 117..120 show that the full 128 bits of the LA are split across 4x 32-bit registers.samarth jain
07/19/2024, 4:54 PMAnton Maurovic (efabless support)
07/19/2024, 5:43 PM// Configure All LA probes as output to the cpu <== !!!note this means output FROM the CPU, and input TO the user design!!!
reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
The intent of setting bits high in the reg_la*_iena
registers is to set those respective lines to actively be outputs from the CPU and thus make them inputs from the perspective of your user project area. Assuming that works, then your user design should see the state of the LA pins as follows, given your most recent code snippet:
• Per line 123: `reg_la1_data = 0x00010000`:
◦ LA[48] = 1
◦ All others in LA[63:32] = 0
• Per line 142: `reg_la3_data = 0x00560000`:
◦ LA[118] = 1
◦ LA[117] = 0
◦ LA[116] = 1
◦ LA[115] = 0
◦ LA[114] = 1
◦ LA[113] = 1Anton Maurovic (efabless support)
07/19/2024, 7:34 PM23116bb8
samarth jain
07/19/2024, 8:05 PMsamarth jain
07/20/2024, 6:57 AMMatt Venn
07/22/2024, 10:45 AM