Hi , I am passing my single cycle riscv rtl code through openlane2 gds2 flow. I am having an issue at global routing stage . it has been showing the following error. as shown in the screen shot_1. on further inspection it shows the following warning " WARNING All instances are FIXED/FIRM. WARNING No need to perform global placement can you help me

@Ahmed Hussain Can you share your verilog?

yeah sure

@Ahmed Hussain Right, your original verilog only had inputs, so during synthesis, I think everything was optimized away. Defining related outputs may fix the problem. Try looking at

./34-openroad-resizertimingpostcts/core.pnl.v

to see where the

clk

and

rst

are connected.

thanks for the response, i have checked core.pnl.v . it is not connected to anything , just defining as input

@Mitch Bailey The clk and rst_n signals are not connected to anything....

so how do we solve it?

Try adding outputs that are dependent on

clk_i

and

rst

.

The issue solved by just declearing the output. Thanks alot for all the support.