Hi there! I am new to openlane2, I am running my riscv single core design through this flow but I am having errors in PDN which can be seen from the attached screenshot. Any one help me with this? Plus, I figure out that if I increase the die area of my design then this error will be resolved but I don't know its still not working maybe I am using wrong syntax in config.json file or something else...

Hi Anis- no, incorrect syntax would be pointed out pretty early on. You can try making your PDN smaller: See https://openlane2.readthedocs.io/en/latest/usage/pdn.html for more info

I have done changes in my config file but now i am getting different error. Can you please comment on this, also I have attached my config file picture as well. @donn

Can you verify your pitch changes in the

resolved.json

file located in the

runs/<timestamp>

directory?

Hi @Mitch Bailey, I have resolved the previous issues using the config file attached, Now I am having issues in global routing. Can you look into this, where I am going wrong.

@Anis Abid I’m thinking that your design may have been synthesized to nothing. Can you share your verilog?

Kindly find the attached file. Maybe you are right because I have coded my riscv isa in system verilog but later changed its extension from .sv to .v file for openlane2. But haven't changed my logic to reg/wire in the code. Also, I have copied all the modules into top module file just to give him one file only. You can have a look at my code. Thanks @Mitch Bailey

@Anis Abid You don't have any outputs for the circuit, so Yosys will simply… optimize it all out. There isn't any area to generate a PDN because there isn't any area. Try exposing some of your signals as outputs…?