@jeffdi Hi Jeff, I received my CLEAR FPGA a few days ago and have since been trying to bring it up together with @Michael Welling! Unfortunately, while the exact same designs work on his board, they don't work on mine. For example, the output of the and_2 design is always high. I tried different bitstreams targeting different I/Os, but no luck. I've looked for any solder bridges on the board, but everything looks fine. Also, I can toggle the I/Os using the mgmt core. Is there anything else I could try?