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FWIW here are some quick place and route visualati...
# clear
m
FWIW here are some quick place and route visualations of the seconds_decoder example as generated for the clear device... due to what appears to be a gui resource linking/embeding issue in the openfgpa toolchain, it is currently necessary for me to build and run vpr as a standalone tool to generate these results.
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f
This is a really cool place and route visualisation !Could you share the method that led to this result?
Thanks for the help. I managed to install and compile vpr and ran vpr starting up without problem. However I have some problem to lauch it on clear example. vpr can't parse architecture XML file vpr_arch.xml. I'm running the vpr command in an run00n directory with following commands (using counter.v as example module) :
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vpr vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH/counter.blif \
  --clock_modeling ideal \
  --device FPGA88 \
  --route_chan_width 60 \
  --absorb_buffer_luts off \
  --write_rr_graph rr_graph_out.xml \
  --disp on
VPR FPGA Placement and Routing.
Version: 8.1.0-dev+v8.0.0-10995-gf13f87b5a-dirty
Revision: v8.0.0-10995-gf13f87b5a-dirty
Compiled: 2024-09-11T22:17:57
Compiler: GNU 11.4.0 on Linux-5.15.0-89-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2

University of Toronto
<http://verilogtorouting.org|verilogtorouting.org>
<mailto:vtr-users@googlegroups.com|vtr-users@googlegroups.com>
This is free open source code under MIT license.

VPR was run with the following command-line:
vpr vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH/counter.blif --clock_modeling ideal --device FPGA88 --route_chan_width 60 --absorb_buffer_luts off --write_rr_graph rr_graph_out.xml --disp on


Architecture file: vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml
Circuit name: counter

# Loading Architecture Description
Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 6: Model 'frac_lut4' output port 'lut2_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 7: Model 'carry_follower' input port 'cin' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 8: Model 'carry_follower' input port 'b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 9: Model 'carry_follower' input port 'a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 10: Model 'carry_follower' output port 'cout' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.00 seconds (max_rss 16.0 MiB, delta_rss +1.2 MiB)
Error 1: vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml:156 Unexpected attribute 'tileable' found on node 'layout'.
The entire flow of VPR took 0.00 seconds (max_rss 16.0 MiB)
m
@Fabien Marteau I'm sorry - I forgot that OpenFPGA makes some additions to the base VPR arch which I manually patched in i.e. (https://openfpga.readthedocs.io/en/master/manual/arch_lang/addon_vpr_syntax/). If you clone and build the master branch of OpenFPGA following their README instructions (https://github.com/lnis-uofu/OpenFPGA) you'l get a standalong vpr binary in the /build/vtr-verilog-to-routing/vpr subdirectory which should understand the attributes mentioned above.
@Fabien Marteau FWIW you have probably already noticed the EZGL library test in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/9eef18c4facb5dad0604682e6e5d3d904b97f6d8/CMakeLists.txt#L39 - when building you'll want to make sure that detection/flag gets enabled either automatically or manually.
From my change list I see I also manually set WITH_BLIFEXPLORER to ON (https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/9eef18c4facb5dad0604682e6e5d3d904b97f6d8/CMakeLists.txt#L52) - but that should only be needed if you maybe want to be able to render the design in a RTL diagram style as well.
Here's my run string (your paths may vary based on the task.conf file settings)
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./OpenFPGA/build/vtr-verilog-to-routing/vpr/vpr ./OpenFPGA_bitstream_generation/openfpga_flow/tasks/SOFA_tasks/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml
./OpenFPGA_bitstream_generation/openfpga_flow/tasks/SOFA_tasks/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/top.blif 
--clock_modeling ideal 
--device FPGA88 
--route_chan_width 60 
--absorb_buffer_luts off 
--write_rr_graph rr_graph_out.xml 
--fix_clusters ./OpenFPGA_bitstream_generation/openfpga_flow/tasks/SOFA_tasks/fix_pins.place 
--disp on
f
I managed to print place&route with VPR \o/ The problem was to use «openfpga» branch of VTR project to support tileable attribute of CLEAR architecture xml description. Has explained by Ganeshgore here.
m
Cool I'll look at that branch too.
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