Hi all, I have a transistor gate in a circuit that is being used as a small capacitor. Things simulated as I wanted and drawing the layout worked out nicely too, but I get a warning when I try to extract the LVS netlist. Is there something I need to do differently to avoid this warning? The LVS works out fine so it looks like things work, but I like my designs clean and without options for the tool to make other interpretations.

@Roel Jordans nfet devices are defined as 4 terminal devices in the tech file. Since the source and drain of the nfet capacitor are connected, there are effectively only 3 terminals. The missing terminal will be connected to GND in your case. You do not generally need to worry about this message.

thanks! that was my guess already but I was hoping for some way to disable the warning for this case since I'll have a design with many more of these and don't want to accidentally miss a more important one

If you use two series transistors, with a floating inner node, the warning disappears.

hmm, that may be an option, I'll see if I can make some space for that

I really need to remove that warning message.