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Hi! I am integrating my macro with top wrapper. ...
# caravel
a
Hi! I am integrating my macro with top wrapper. I am facing error at floorplan stage. Can anyone help me to remove this problem.
m
Can't read the screen shot, but looks like something is missing from 
EXTRA_LEFS
c
I would like to read the 
module ????? not found
section clearly.
m
If you could attach the error log and 
config.tcl
file, we might be able to provide a more helpful response.
a
@Mitch Bailey @Cra2yPierr0t[INFO]: current step index: 4 [ERROR]: Floorplanning failed [ERROR]: module aes1281 not found in /home/shahid/caravel_user_project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef [ERROR]: Check whether EXTRA_LEFS is set appropriately [INFO]: Calculating Runtime From the Start... [INFO]: flow failed for user_project_wrapper/2022.08.16_15.35.06 in 0h0m16s [INFO]: Generating Final Summary Report... [INFO]: Design Name: user_project_wrapper Run Directory: /home/shahid/caravel_user_project/openlane/user_project_wrapper/runs/user_project_wrapper Source not found. ---------------------------------------- LVS Summary: Source: /home/shahid/caravel_user_project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs_parsed.gds.log Source not found. ---------------------------------------- Antenna Summary: No antenna report found. [INFO]: check full report here: /home/shahid/caravel_user_project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv [INFO]: Saving Runtime Environment [ERROR]: Flow Failed.
This is the log file information.
I have successfully created the GDS and LEF file of my macro, I am facing the problem during implemention of the top wrapper.
Config.tcl
set ::env(PDK) "sky130A"
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl # YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl set script_dir [file dirname [file normalize [info script]]] set ::env(DESIGN_NAME) user_project_wrapper #section end # User Configurations ## Source Verilog Files set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/user_project_wrapper.v" ## Clock configurations set ::env(CLOCK_PORT) "clk" set ::env(CLOCK_NET) "clk" set ::env(CLOCK_PERIOD) "100" ## Internal Macros ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ count1 vccd1 vssd1" ### Macro Placement set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/user_proj_example.v" set ::env(RUN_CVC) 1 set ::env(EXTRA_LEFS) "\ $script_dir/../../lef/user_proj_example.lef \ $script_dir/../../lef/aes1281.lef" set ::env(EXTRA_GDS_FILES) "\ $script_dir/../../gds/user_proj_example.gds \ $script_dir/../../gds/aes1281.gds" #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} # disable pdn check nodes becuase it hangs with multiple power domains. # any issue with pdn connections will be flagged with LVS so it is not a critical check. set ::env(FP_PDN_CHECK_NODES) 0 # The following is because there are no std cells in the example wrapper project. set ::env(SYNTH_TOP_LEVEL) 1 set ::env(PL_RANDOM_GLB_PLACEMENT) 1 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 set ::env(FP_PDN_ENABLE_RAILS) 0 set ::env(DIODE_INSERTION_STRATEGY) 3 set ::env(FILL_INSERTION) 0
m
Does 
/home/shahid/caravel_user_project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
contain 
aes1281
?
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