<@U03DNPRUBFD> Also try to change integration meth...
# analog-design
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@Faedra Webers Also try to change integration method, may be to backward euler (
.options Method=trap maxord=1
). Also increase ITL4 (ITL4=200). "_MAXORD=x [*] specifies the maximum order for the numerical integration method_ used by SPICE. Possible values for the Gear method are from 2 (the default) to 6. Using the value 1 with the trapezoidal method specifies backward Euler integration. METHOD=name sets the numerical integration method used by SPICE. Possible names are ‘Gear’ or ‘trapezoidal’ (or just ‘trap’). The default is trapezoidal. ITL4=x resets the transient analysis time-point iteration limit. The default is 10. _CHGTOL=x resets the charge tolerance of the program. The default value is 1.0e-14._"
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Thank you for your reply! I tried your settings, and the result stayed the same. I tried to increase them even further ITL4= 1000 and CHGTOL = 10e-18 , but simulation is still running after 2 hours...
s
@Faedra Webers another thing to test is the .tran timestep. The tran (or .tran) command accept up to 4 parameters: .tran <tstep><tstop> [<tstart> <tmax>] you can try to lower tstep and tmax (and reset CHGTOL and ITL4 to less aggressive values)
If you still see nodes diverging may be there is a off-state leakage problem? try to increase the channel length of transistors or replace _lvt with standard transistors.
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