Hi , Is there any way to mention skew targets for different registers ? -- Fo example , i have 3 regs in my design clocked by CLK - A_reg , B_reg , C_reg .. The requirement is that the skews (clock edge reaching time) is difference of 1ns. ie. Launch latency of A_reg by default CTS is eg ~1ns. Then B_reg latency should be 2ns and c_reg should be 3ns. Thanks

There is probably no way of doing it. But you can use eco flow to add additional delays to the CTS of that registers. However, it is a very specific request. Why would you need it?

I would need to time the control registers, These ctrl regs , go out to a MACRO pins (analog) Now this cannot be done with pipeline since it will cause addition cycle delay. I can add buffers , but i hoped CTS tool should have had a set_target_latency type option to specific hierarchy . registers.

the insert buffer flow i guess will work . but the only issue if the registers are busses - then would need to find out the common point , else inserting for every register will add extra buffers....

You are doing a rare edge case usage of the flow. There is going to be a lot of issues related to that. If I was doing it, I would make an OpenLane macro that would handle the registering and delay. Then would repeat for each bus. ... Or just do the proper way and use analog flow for this purpose. It's unlikely that your delay will be that precise, considering in sky130 there is ~50% deviation in delay between worst and best case. Therefore macro will provide the flexibility + you can make it configurable delay.

yes . i was trying to avoid the way you were mentioning... if there was any tool option , then i was looking into delaying the capture clock , rather than the delaying the data bus afterwards...