Hi @Tim Edwards, I think there is possibly a bug in the substrate extraction introduced with magic 8.3.274. Starting then, magic starts to extract transistor bodies connected to the substrate as separate nodes in my design. Here is an example that passes on 8.3.270 and fails on 8.3.274. 8.3.271-8.3.273 also fail but for reasons that seem to be fixed in 8.3.274. tmp/run_ext.sh reruns magic extraction and tmp/run_lvs.sh reruns lvs. I am on the most recent netgen 1.5.227.

Jesse, I believe this has been fixed in more recent versions. Can you install the latest version?

I have tried on the most recent version 8.3.315 and 8.3.274 is the first version that produces this result

Thanks for checking the version numbers. I'll take a look.

Oh sorry, that was from one of my debugging attempts. Even if I remove all the nwell drawing/pin/labels from those regions and add pwell drawing I get the same result. I even added a giant pwell drawing the extended the whole column and they were still disconnected in the lvs. I can send that too if it is helpful

Following thread.

I don't think adding pwell drawing makes a difference. See https://open-source-silicon.slack.com/archives/C016YSAP6TZ/p1654867601538659?thread_ts=1654808966.464369&cid=C016YSAP6TZ As you are probably aware, magic is not as 'versatile' as commercial tools when it comes to extracting hierarchies. Commercial tools can heuristically determine when to flatten cells or push layers down the hierarchy whereas magic tries to extract the layout hierarchy as is. This causes problems when all the device layers do not exist at the same hierarchy. I deal with this by flattening the 'aberrant' cells during gdsin. Your

run_ext.sh

script has the following lines which you would expect to flatten pcells and sparse cells,

gds flatglob *_?mos_m*
gds flatten true

but the following line prevents flattening.

gds readonly true

Since this is only temporary magic data, you can remove this line. If you examine the contents of the directory with

.ext

files, you should no longer see sparse cells like

sky130_fd_bd_sram__sram_sp_cell_fom_serif_nmos.ext

. I would suggest flattening any cells that do not have text and any cells that have unconnected conductive layers. These cells do not have text (from your extracted

*.spice

file).

sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce
sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce

This cell also has

dnwell

with no connections at that hierarchy. This may be what is causing your psub problem. Be aware that

dnwell

not completely surrounded by

nwell

at every extracted level will not extract as hoped.

sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce

Thanks for the detailed response! I'll try out these changes tomorrow

Tagging @Tim Edwards just so you're aware of the discussion.

I wonder if these rules should be a part of the PDK...