I'm working on a proof of concept to create a mixe...
# openlane-2
w
I'm working on a proof of concept to create a mixed signal design using OpenLane 2. I'm encountering an issue with routing the power pins dvdd and dvss; the image shows that they aren't being connected. All the files I'm using are listed below, and it's worth mentioning that I'm skipping some steps in OpenLane's standard synthesis flow to reach the end of the flow. Does anyone have any ideas on what I could do to make these connections?
m
Does adding this to the
config.json
file make a difference?
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"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
w
Unfortunately not
m
Sorry ’bout that. Looks like that’s no longer needed in openlane2.
Your lef file looks really intricate. I don’t know that you need
nwell
or
li1
in there. You might try remaking the lef file with the magic command
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lef write -hide -pinonly <top_cell>.lef
w
We've already tried to do that, but then openLane stop at step 19 (Power Distribution Network Generation). It throws error PDN-0233 - Failed to generate full power grid.
m
@William Carrara Orlato openlane has 2 macro halo settings. https://openlane2.readthedocs.io/en/latest/reference/step_config_vars.html
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FP_MACRO_HORIZONTAL_HALO
FP_MACRO_VERTICAL_HALO
The default values are 10um which matches your layout, I think. A “usual” implementation of hardened macros would only use (for example) up to metal4 for all the macro power rails and then the power routing would be metal5 horizontal across the top, dropping via4 on to the metal4 power rails in the macro. In your case, dvdd is on metal5, dvss is on metal4, avdd is metal2 and avss is metal1.
Maybe this helps. https://openlane2.readthedocs.io/en/latest/usage/pdn.html Remember power is not routed like signals. Power rails must be used in a configuration where there can be overlap.
The layout is using
avdd
and
avss
. Those power signals are not in the current verilog or config file.
w
Hello @Mitch Bailey, thank you for your help. We've conducted several additional tests, but we're still having trouble routing the power lines. We've completely changed our approach; now we're trying to generate a "Wrapper" for the analog circuit and then integrate it with the digital one. However, the power lines still aren't connecting to the circuit. Do you know what might be going wrong? Below is the configuration and an image of the circuit.
image.png
m
@William Carrara Orlato I think you’re on the right track! I’m not an expert on the openlane2 configuration variables yet, but I think when you use json lists for
PDN_MACRO_CONNECTIONS
, that you need to delimit each connection with a
,
.
@donn is that correct? I didn’t see any examples here but if the format is the same as openlane, either of the following should work: “PDN_MACRO_CONNECTIONS”: [“analog vdda1 vssa1 avdd avss,“, “analog vccd1 vssd1 dvdd dvss”], “PDN_MACRO_CONNECTIONS”: “analog vdda1 vssa1 avdd avss, analog vccd1 vssd1 dvdd dvss”, (edit: the openlane format probably does not work with openlane2. You’re current settings should work.). From your screen shot, you can see that the parent level power routing extends across the entire macro, just as you want. I think the problem is that the met1 macro power rails are buried under met2 obstruction, so openlane can not place vias there. Can you try changing the last met2 obstruction in the lef file from
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LAYER met2 ;
        RECT -107.845 53.545 137.435 87.505 ;
        RECT -107.845 52.095 115.700 53.545 ;
        RECT 120.670 52.095 137.435 53.545 ;
        RECT -107.845 29.985 137.435 52.095 ;
        RECT -107.845 28.825 118.660 29.985 ;
        RECT 120.670 28.825 137.435 29.985 ;
        RECT -107.845 -11.340 137.435 28.825 ;
to
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LAYER met2 ;
        RECT -107.845 53.545 137.435 87.505 ;
        RECT -107.845 52.095 115.700 53.545 ;
        RECT 120.670 52.095 137.435 53.545 ;
        RECT -107.845 29.985 137.435 52.095 ;
        RECT -107.845 28.825 118.660 29.985 ;
        RECT 120.670 28.825 137.435 29.985 ;
        RECT -93.0 -11.340 122.0 28.825 ;
Hopefully, this will uncover the met1 power rails and allow all the layers for the metal5 - metal1 connections. In openlane, I think you need to modify the
pdn.tcl
file to handle dropping vias across multiple layers. I don’t know if openlane2 will handle that automatically or not. Are the power connections the only problem you’re having now?
d
you can omit the weird comma in openlane2 iirc
👍 1
w
Thank you very much for helping, but just changing the .lef also didn't work. Do you have any idea where to start in this 'pnd.tcl' file? Any documentation?
m
This looks similar to designs @Mehdi has done so perhaps he can advise.