So, on TT05 there was a test analog design from JKU / @Harald Pretl. Among other things, it had a loopback that would connect two pins through a transmission gate. I made a PEX of that design, I then added some resistance in the simulated path ( 250 ohm for each signal ) to account for the 150 ohm of the analog pad connection and then ~100 ohm of wiring (it's on

met3/met4

with a few vias, doesn't go very far but it's also fairly thin traces). I measured the segments in klayout then used sheet resistance and came up with the 100 ohm figure. Now I simulate this in ngspice, just looking at the DC resistance. Basically I check how much voltage a 10uA current generates across the pins (with one of them grounded since the resistance of the transmission gate will depend on the bias level). Simulation shows around 1.2 kOhm (i.e. about 12 mV across the pins). I now do the same test but on the real silicon using a Keithley 2400 SMU. Instead I get about 24 mV or twice the expected value. It's definitely not noise, I averaged, verified reading with multimeters, it all checks out. So now the question is : Where did I screw up ? What did I forget to account for ? Corners / Temperature / VDD ... all show some variations of course, but nowhere even close to that 2x factors even combining all of those.

Run a DC sweep from ground to supply voltage with a voltage source, instead of a fixed current source. Measure the currents. They should be very non linear.

@Luis Henrique Rodovalho Well I ran a bias sweep over the whole range. (Again, fixed current, between the pins, but instead of connected to ground, I varied voltage ). https://images-ext-1.discordapp.net/external/TORcikyt47zyIyZjeI-eSFp6B4Naa7upQUw5szOuAaI/h[…].png?format=webp&quality=lossless&width=1118&height=687

What is the voltage at the other end of the transmission gate?

Just ... not the absolute value. I'm not too worried about the peak value (because this is where the transmission gate transition from the Nmos doing most of the work to the Pmos doing most of the work and this is heavily influenced by the Vth of those and where they cross).

If you run that with SS and FF corners you would have another curve

I did. It doesn't change much.

Well... It is what it is. At least it works as an analog switch. Maybe the problems are the models. Who knows?

The peak value vary the most. But as I said, I'm not too concerned about the peak. I'm more looking at explaining the value on the left side of the graph where things should be more stable.

In a real application, the voltage drop shouldn't be large. It is just a simulation for a short circuit case.

I'm more concerned with the AC bandwidth. I have to drive the capacitive load at the output through it.

And there are high speed analog signals... That would be a problem too...

And AC testing shows a bandwidth lower than expected about in the same order of magnitude than my DC resistance is higher than expected.

Ok. For your testbench, you should make the too terminals of the transmission gate at the same voltage and run a AC sim, injecting a AC voltage at one side. Measure the AC current and you will have the AC resistance

That's why I'm looking at DC now, less things should matter and between 1.2k (sim) and 2.4k (measured), I'm pretty sure the bond wires are not 1kOhm. But if I can't trust sim to that level, I might as well do things blindly ...

Are those DC curves? Are you calculating the resistance using derivatives?

I'm calculating resistance because I know I'm feeding 10 uA and I get 25 mV across the pins.

This doesn't work for non linear circuits.

Why ? I admit there will be a small error, but the voltage difference developped by 10uA is tiny and the resistance is almost constant locally, especially at the "edge" of the graph (away from the peak and of most of the non linearity).

https://en.m.wikipedia.org/wiki/Electrical_resistance_and_conductance See Static and differential resistance

Heh, except I need to know if the difference comes from the transmission gate, the models or from me not modelling something. There are many changes between shuttles and I'm trying to predict performances / specs for the next ones so what I'm looking for is the ability to build devices that turn out as intended 🙂 That TG itself won't ever be used again, that was a test one. We had a gen 2 on TT6 and then a gen 3 on TT7 ... but those will only come back in several months.

@tnt: I'm late to the discussion here, but my take on this is that you should see a 2x difference (or more) across corners, if you use the resistance and capacitance low/high corners (high, specifically, for this case). Magic can extract the high corner if you use

extract style ngspice(hrhc)

. For example, the p-diffusion contact resistance is 585 ohms at the nominal corner, but 840 ohms at the high corner. For device resistance and capacitance (not parasitics), use the High-High simulation corner

.lib sky130.lib.spice hh

. Note that the

sky130.lib.spice

file uses nominal transistor corners when specifying the resistor/capacitor corner, so if you wanted to look at

hh

+

ss

, you would need to construct your own

.lib

entry with the appropriate file includes.

@Tim Edwards Interesting, thanks. I will re-reun PEX with hh. And indeed this is not openframe yet, which already surprised me on the digital signal because I still thought that there was a still a small digital block near each IO that was for instance just buffering

in

signal with a strong

buf_16

but I found out that now it's all one large logic blob and that not only it's only a

_4

strength buffer now, but openlane also explicitely added

dly

cells on the path 😑 . I didn't know the

analog

connection also had such routing done in the wrapper.

I was looking only at the wrapper cell itself. I take it you're looking at the routing between the user project area and the padframe? That's also bad due to using equal spacing between pins on the user wrapper boundary, causing some pins on the user project to be pretty far away from the GPIO pad they're connected to (and routed using minimum width wiring and single vias).

Yeah, I'm looking at the pin we connect to (from user_project_wrapper) to the actual pad on the pad frame. I had not accounted for that, I had only counted the routing inside the user_project_wrapper itself.

I have complained multiple times that the openlane routing is not appropriate for analog. . .

I'll remodel to account for all of it and I'm pretty sure that'll explain the difference. Thanks, that's exactly the kind of stuff I was looking for and that I completely overlooked when simulating.

I got bitten by the same problem on our first test chip with a DAC and ADC; the analog blocks were first placed far away from the pads, and then the output was routed through the middle of the SoC digital to get to the pad. That resulted in about a 1.5 lsb offset on the DAC output and about 20 lsb of digital noise on the output.

Oh wow, 20 LSB yikes.

I saw that, too, but decided it was not worth complaining about. The diodes will tolerate 5V+.

Ok, good to know.