Cra2yPierr0t
08/07/2022, 1:42 PMdependencies/pdks/sky130B/libs.ref/sky130_sram_macros
to their design in Caravel on mpw-7a?
I get Check whether EXTRA_LEFS is set appropriately
with Caravel, and I get an LVS error when I build OpenLANE by itself.
If anyone was able to add the sram macro to their design, please show me the repository or config.tcl.Matt Venn
08/07/2022, 2:31 PMMitch Bailey
08/07/2022, 3:14 PMEXTRA_LEFS
set in config.tcl
?Cra2yPierr0t
08/07/2022, 5:05 PMmodule $not found in merged.nom.lef
. I have copied the .gds, .v and .lef to caravel.Matt Venn
08/07/2022, 5:07 PMMitch Bailey
08/07/2022, 5:32 PM$script_dir
has had some issues when used with older versions.
Can you do a puts $::env(EXTRA_LEFS)
afterwards to make sure it's where you expect it to be?
You might also check the config.tcl
file in the runs/<tag>/
directory. That should contain the expanded version.Mitch Bailey
08/07/2022, 5:40 PM$script_dir/../../
, use $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macos/
.
If you've copied the files to <design>/caravel
, and your $script_dir
is <design>/openlane/<macro>
, $script_dir/../../
would refer to the <design>
directory and not <design>/caravel
.
Or have you copied the files to <design>/verilog/rtl
, <design>/lef
and <design>/gds
respectively?Cra2yPierr0t
08/07/2022, 5:48 PM$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macos/
but the result did not change.Cra2yPierr0t
08/07/2022, 5:53 PMMitch Bailey
08/07/2022, 6:06 PMuser_project_wrapper
? The one in the repo doesn't appear to match the rtl verilog (one sram instance).
I'm thinking that the $not
module might refer to the inverter needed to create the inverted signal for
.csb0 (~wbs_stb_i ), // active low chip select
.web0 (~wbs_we_i ), // active low write control
I think you have SYNTH_TOP_LEVEL set to 1 which won't do synthesis, correct?
Maybe instead of inverted signals, you could test with non-inverted signals.Cra2yPierr0t
08/07/2022, 6:18 PM