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[ERROR]: during executing openroad script /openlan...
# sky130
b
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer_routing_timing.tcl [ERROR]: Log: designs/nonlimited/runs/RUN_2022.08.06_19.19.09/logs/routing/16-resizer.log [ERROR]: Last 10 lines: met4 524533 0 0.00% 0 / 0 / 0 --------------------------------------------------------------------------------------- Total 4261499 0 0.00% 0 / 0 / 0 [INFO GRT-0018] Total wirelength: 0 um [INFO GRT-0014] Routed nets: 0 [INFO]: Setting RC values... [ERROR RSZ-0005] Run global_route before estimating parasitics for global routing. Error: resizer_routing_timing.tcl, 59 RSZ-0005 child process exited abnormally [ERROR]: Creating issue reproducible...
m
it seems like global routing must have failed before this step was reached. Are there any GRT errors?
b
There doesn't seem to be any errors other than the ones I've shared.
Here is the my config.tcl file if you need to analyze.
config.tcl
a
::env(SYNTH_USE_PG_PINS_DEFINES) "USE POWER PINS" Spaces are not allowed afaik
There is so much things wrong with this config, I am not even sure where to start
Line 23 is definetly wrong.
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set ::env(RT_MAXLAYER) 4
set ::env(RT_MINLAYER) 1
Why?
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set ::env(DECAP_CELL) "
Why?
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::env(GRT_MAXLAYER)
Why is it higher than RT_MAXLAYER?
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set ::env(PL_TIME_DRIVEN) 0
Why?
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set ::env(PL_MAX_DISPLACEMENT_X) 1000
set ::env(PL_MAX_DISPLACEMENT_Y) 1000
That's unreasonably high values
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set ::env(CTS_TARGET_SKEW) 150
set ::env(CTS_TOLERANCE) 25
Why?
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set ::env(CLOCK_BUFFER_FANOUT) "3"
Why?
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DRT_OPT_ITERS
Minor, but regardless why reduce it?
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GLB_RT_TILES
This has no effect, why is it set?
Can you post full logs?
b
Actually, I am beginner at openlane. I try to write default settings using openlane configuration settings. Except some of config settings, I don't know how to do setting for configs.
a
You can follow simple rule: Take the bare minimum config. Which is defined according to configuration: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/configuration/README.md#required-variables Run and test if it works. After each step, you can start adding/changing the options as you need.
Everything that is not required has a default value. The values have been tested and known to work. Read the documentation and follow the guide in openlane's RTD: https://openlane.readthedocs.io/
b
Thank you for your reply. I set only general configurations. I try to run like this commands.
# User Config set ::env(DESIGN_NAME) {CPU} #Change if needed set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/*.v" #Fill this set ::env(CLOCK_PERIOD) "20.0" set ::env(CLOCK_NET) "clk_i" set ::env(CLOCK_PORT) "clk_i" set ::env(PDK) "sky130A" set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" set ::env(DESIGN_IS_CORE) 0
However I got some power delivery network errors. I share it.
[ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl [ERROR]: Log: designs/nonlimited/runs/RUN_2022.08.07_08.09.27/logs/floorplan/6-pdn.log [ERROR]: Last 10 lines: [INFO ODB-0225] Created 441 library cells [INFO ODB-0226] Finished LEF file: /openlane/designs/nonlimited/runs/RUN_2022.08.07_08.09.27/tmp/merged.nom.lef [INFO ODB-0127] Reading DEF file: /openlane/designs/nonlimited/runs/RUN_2022.08.07_08.09.27/results/floorplan/CPU.def [INFO ODB-0128] Design: CPU [INFO ODB-0130] Created 2 pins. [INFO ODB-0133] Created 2 nets and 0 connections. [INFO ODB-0134] Finished DEF file: /openlane/designs/nonlimited/runs/RUN_2022.08.07_08.09.27/results/floorplan/CPU.def [ERROR PDN-0108] Spacing (-0.2200 um) specified for layer met4 is less than minimum spacing (0.3000 um). Error: pdn_cfg.tcl, 123 PDN-0108 child process exited abnormally [ERROR]: Creating issue reproducible... [INFO]: Saving runtime environment... OpenLane TCL Issue Packager
I added pdn settings in my config.tcl. However I got errors like in my first post that I share.
a
Can you post the verilog too?
Looks like the design is too small.
Typically the designs going through openlane are big enough for this type of issues to not rise. Try setting FP_SIZING to absolute and DIE_AREA to "0 0 400 400" This will make the PDN big enough so it will not have issue then
b
Actually, I added fp_sizing and die_area in my file. Here is the last form in my file.
# User Config set ::env(DESIGN_NAME) {CPU} #Change if needed set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/*.v" #Fill this set ::env(CLOCK_PERIOD) "20.0" set ::env(CLOCK_NET) "clk_i" set ::env(CLOCK_PORT) "clk_i" set ::env(PDK) "sky130A" set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" set ::env(DESIGN_IS_CORE) 0 # ### Power Nets # # You can draw more power domains if you need to set ::env(VDD_NETS) [list {vccd1}] set ::env(GND_NETS) [list {vssd1}] set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 3000 3000" set ::env(FP_CORE_UTIL) 18 set ::env(DESIGN_IS_CORE) 1
Here is the fulloutput of error.
STEP 1] [INFO]: Running Synthesis... [STEP 2] [INFO]: Running Single-Corner Static Timing Analysis... [INFO]: Creating a netlist with power/ground pins. [STEP 3] [INFO]: Running Initial Floorplanning... [INFO]: Extracting core dimensions... [INFO]: Set CORE_WIDTH to 2988.62, CORE_HEIGHT to 2975.68. [STEP 4] [INFO]: Running IO Placement... [STEP 5] [INFO]: Running Tap/Decap Insertion... [INFO]: Power planning with power {vccd1} and ground {vssd1}... [STEP 6] [INFO]: Generating PDN... [STEP 7] [INFO]: Running Global Placement... [STEP 8] [INFO]: Running Placement Resizer Design Optimizations... [STEP 9] [INFO]: Writing Verilog... [STEP 10] [INFO]: Removing Buffers from Ports (If Applicable)... [STEP 11] [INFO]: Running Detailed Placement... [STEP 12] [INFO]: Running Clock Tree Synthesis (logging to 'designs/nonlimited/runs/RUN_2022.08.07_08.27.53/logs/cts/12-cts.log')... [STEP 13] [INFO]: Writing Verilog... [STEP 14] [INFO]: Running Placement Resizer Timing Optimizations... [STEP 15] [INFO]: Writing Verilog... [INFO]: Routing... [STEP 16] [INFO]: Running Global Routing Resizer Timing Optimizations... [ERROR]: during executing openroad script /openlane/scripts/openroad/resizer_routing_timing.tcl [ERROR]: Log: designs/nonlimited/runs/RUN_2022.08.07_08.27.53/logs/routing/16-resizer.log [ERROR]: Last 10 lines: met5 187922 0 0.00% 0 / 0 / 0 --------------------------------------------------------------------------------------- Total 6308432 0 0.00% 0 / 0 / 0 [INFO GRT-0018] Total wirelength: 0 um [INFO GRT-0014] Routed nets: 0 [INFO]: Setting RC values... [ERROR RSZ-0005] Run global_route before estimating parasitics for global routing. Error: resizer_routing_timing.tcl, 59 RSZ-0005 child process exited abnormally [ERROR]: Creating issue reproducible... [INFO]: Saving runtime environment... OpenLane TCL Issue Packager
What can I do to overcome error for this step?
a
Can you post verilog? Seems the CPU module has 2 pins and nets but zero components.
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[INFO ODB-0128] Design: CPU
[INFO ODB-0130]     Created 2 pins.
[INFO ODB-0133]     Created 2 nets and 0 connections
Also 3000 um x 3000 um is unreasonably high. The runtime and RAM usage is going to be huge. Set it to max 1000 x 1000, even better 500 x 500 if you design is small.
b
Can you please share your e-mail address for sending files?
I have decreased the die area from the "3000 3000" to the "500 500". However, I got the same errors. Which I write essential global routing commands for overcome this error?
a
1. Version of OpenLane 2. Post the verilogs on GitHub issues, maybe here: https://github.com/armleo/OpenLane 3. "Which I write essential global routing commands for overcome this error?" We need to figure out why it thinks the CPU module has zero components. You cant route an empty component right?
b
I don't understand that why I have zero components or zero routed nets for CPU. What is the main cause of error?
a
Can you post at least the top level verilog here as attached file?
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