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comp.out

buff_4_magic.spice

buff_4_xschem.spice

Thanks <@U01819B63HP>, I added a tap cell in the layout and added VDD and GND pins in xschem but the lvs still fails

1. In your spice netlist generated by xschem you dont have buff_4 cell, yet you are comparing buff_4 from spice netlist with the buff_4 from magic extracted netlist

2. You did not attache the layout so its not clear what you are comparing. There is a chance that you dont have the tap cells that are required to connect nwell and pwell to vdd and vss respectively

3. The original xschem netlist does not include the cell from hd library. It will try to treat it like a blackbox, but will always fail because it does not know the names of the pins

buff_4 schematic.png

buff_4 layout1.png

buff_4 layout2.png

1. There's a buff_4 subcircuit in the xschem netlist although it's instantiated as x1 by default. Not sure if that's the problem.
2. Attached the layout and schematic 
3. Should I have an include statement in xschem schematic to point to the library?

<@U02FS8M47FX> try to manually include this netlist at the end of the xschem spice netlist:
```.subckt sky130_fd_sc_hd__buf_4 A VGND VNB VPB VPWR X
X0 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X1 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X2 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X3 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X4 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X5 a_27_47# A VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X6 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X7 a_27_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X8 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X9 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
.ends```
This is from `.../share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice`

1.png

<@U02FS8M47FX> if this works try a more general approach: include the spice netlist of all cells with a .include line. Netgen will use only the used cells. Add a `code.sym` symbol as shown with the following attributes:
```name=TT_MODELS
only_toplevel=true
format="tcleval( @value )"
value=".lib $::SKYWATER_MODELS/sky130.lib.spice tt
.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice
"
spice_ignore=false```