Matt, in my search for a solution of the above problems, I’ve seen that you guys are active with another testchip. So let me share some simulation results: 1) The minimum clock pulse width is < 1.5 nsec. Would be great if you could stimulate such a pulse. 2) Data out valid from neg clock edge is around 1.3 – 3 nsec. Obviously capacity dependent. 3) Read and write during same cycle is problematic for small SRAMs (e.g. of the size of a register file). I propose to check this on silicon. It would be a pity if user rely on this feature. Here are more details. Xsky130_sram_4kbytes_1w1r_16x2048_8: output delay: * 1.00f: rise: 50%: 1.66ns 90%: 2.58ns *27.56f: rise: 50%: 2.55ns 90%: 2.79ns pulse-width: 1.25 ns worked 1.00 ns failed Xsky130_sram_64bytes_1w1r_32x16_8: read/write error !!! output delay: * 1.00f: rise: 50%: 1.37ns 90%: 2.38ns *27.56f: rise: 50%: 2.29ns 90%: 2.52ns pulse-width: 1.00ns worked 0.75ns failed Cheers, Tobias (bearbeitet)

1-2) Yes we have simulation capability for this. We will be adding stand-alone utilities to do it on existing memories. I'm waiting on my student to merge this... 3) This is why we mention it in the Verilog model as a warning: $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1); We would definitely like to add a check on this to see if it is allowable, but you are right that small memories may have issues.

1-2) These are my simulation result, which I use to design my project. The suggestion I wanted to make was, that you design your testchip accordingly (clock generation, etc.), so that you can verify these numbers on silicon. We are talking about 300MHz plus. 3) We had this discussion before, and if I understand it correctly, based on that Andrew added some tests for this during silicon characterization. The understanding at that time was, that writes\reads at the same cycle are valid. But I simulated it afterwards and found problems for small SRAMs (RF-size). So my proposal would be to include a small SRAM on the testchip to verify this behavior on silicon.

We are doing what we can.