Cheers, in my project (7a) I’m down to 0 FEOL and 25 BEOL violations. It is an RTL project only, so no manual layout modifications done. The placement density is very low. 24: m1.7 [user_proj_example] m1.7 : min. m1 with holes area : 0.14um² 1: m2.7 [user_proj_example] m2.7 : min. m2 holes area : 0.14um² polygon: (918,517.21;918,517.43;918.26,517.43;918.26,517.21) What would be the recommended strategy to tackle these violations ? Thank you for your help in advance.

Several discussions of this issue in the past month. See https://open-source-silicon.slack.com/archives/C016H8WJMBR/p1658758347451059

@Mitch Bailey Thanks, I just thought it had been fixed already and this is another problem. @donn @Tim Edwards Do you guys think, that "the" m1.7 and m2.7 issues should be "fixed" in a PDK downloaded yesterday ?