module test;
wire qq;
reg ck, dd, ss;
sky130_fd_sc_hd__dfstp_2 1836 (
.CLK(ck),
.D(dd),
.Q(qq),
.SET_B(ss)
);
always
#5 ck = ~ck;
initial begin
$monitor($time," TEST DISPLAY = %b %b %b %b", ck, dd, qq, ss);
ck = 0; dd = 0; ss = 0;
#20 ss = 1;
#100 $finish;
end
endmodule
~
The above is a small test case using a dff cell from sky130 fd_sc_hd. Compiled as follows:
iverilog test.v ./dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/verilog/*.v. The simulation result shows that the output q is always x. How to resolve this?
@DESKTOP-6TA75K4:~/projects/rtl_efab$> ./a.out
ck d q ss
0 TEST DISPLAY = 0 0 x 0
5 TEST DISPLAY = 1 0 x 0
10 TEST DISPLAY = 0 0 x 0
15 TEST DISPLAY = 1 0 x 0
20 TEST DISPLAY = 0 0 x 1
25 TEST DISPLAY = 1 0 x 1
30 TEST DISPLAY = 0 0 x 1
35 TEST DISPLAY = 1 0 x 1
40 TEST DISPLAY = 0 0 x 1
45 TEST DISPLAY = 1 0 x 1
50 TEST DISPLAY = 0 0 x 1
55 TEST DISPLAY = 1 0 x 1
60 TEST DISPLAY = 0 0 x 1
65 TEST DISPLAY = 1 0 x 1
70 TEST DISPLAY = 0 0 x 1
75 TEST DISPLAY = 1 0 x 1
80 TEST DISPLAY = 0 0 x 1
85 TEST DISPLAY = 1 0 x 1
90 TEST DISPLAY = 0 0 x 1
95 TEST DISPLAY = 1 0 x 1
100 TEST DISPLAY = 0 0 x 1
105 TEST DISPLAY = 1 0 x 1
110 TEST DISPLAY = 0 0 x 1
115 TEST DISPLAY = 1 0 x 1
test.v21 $finish called at 120000000000000 (1ps)
120 TEST DISPLAY = 0 0 x 1