hi, I got error on STEP 37 Running LEF LVS: [ERROR]: There are LVS errors in the design: See '../signoff/37-core_region.lvs.lef.log' for details I looked at this document: ----------------- LVS reports: net count difference = 4 device count difference = 0 unmatched nets = 2257 unmatched devices = 228 unmatched pins = 0 property failures = 0 Total errors = 2489 ----------------- There are mismatches when I looked at core_region_lef.log file, but couldn't understand why I attached config.tcl, lef.log and core_region.lef.log files

Looks like your sram macros aren't connected to power. See your connection counts

Number of nets: 35486 **Mismatch**         |Number of nets: 35482 **Mismatch**

Layout's on the left and schematic/verilog is on the right. More nets in the layout generally means something is not connected. In the long list of unmatched nets, you'll find vssd1 and vccd1 entries. In the layout, you can see the unconnected vssd1 nets here

Net: data_mem.open_ram_2k/vssd1            |Net: _noconnect_228_
  sky130_sram_2kbyte_1rw1r_32x512_8/vssd1  |  sky130_fd_sc_hd__conb_1/HI = 1
...
Net: instr_mem.sp_ram_wrap_i.open_ram_2k/v |Net: _noconnect_235_
  sky130_sram_2kbyte_1rw1r_32x512_8/vssd1  |  sky130_fd_sc_hd__conb_1/HI = 1

himm thanks, I am trying to understand power connection, do I need to provide vssd1 and vccd1 pins to all the sub-modules inside the top module? I found my mistake about SRAM macros. It was missing pins in the hierarchy. But do I need to connect power pins all my sub-modules other than SRAM macros?

In your

config.tcl

file add a power connection line for each macro.

set ::env(FP_PDN_MACRO_HOOKS) "\
	macro1 vccd1 vssd1 VPWR VGND,
	top.macro2 vccd2 vssd2 vccd2 vssd2"

where the macro name is the hierarchical name from verilog

thanks, but other than macros I don't need to add power pins to any RTL modules right?

standard cells are powered handled automatically. I believe you only have to specify macros in

FP_PDN_MACRO_HOOKS

.

OK thanks I will rerun the flow with power connections. well even though openroad github has a motto of "OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS)" it is more than 24-hour, I can assure anyone 😄

What are you running on and how many gates does your design have?

it is a riscv core with 2K instr and data memories. I am trying to harden this as a macro, and then I will add a bus and peripherals I am new to ASIC area, come from FPGA sector and trying to learn with openlane synth results are: Number of wires: 28706 Number of wire bits: 29964 Number of public wires: 4386 Number of public wire bits: 5644 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 29128

It doesn't seem like that big of a design. Maybe there are problems routing around the sram that take time. I don't know if changing the placement would make a difference in run time or not.

I redesigned the RTL and exclude OpenRAM macros from it and added memory ports to the module to connect OpenRAM. After that it finished the flow successfully. I see that almost all the designs in MPW shuttles, first harden macros that are utilizing standard cells, then in the wrapper verilog code only connect these macros. I also will bu using this method for MPW7 shuttle. I had very bad memories using macros with standard cells to harden a macro, I don't suggest it :l