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<@U02NGKNUN5V> Can you send me the complete netlist for the first example (connect each bit to the ADC bridge)?

it wrapped up in some symbols, where the schematic just contains the xspice code:

image.png

`x1 net3 IN[2] VREF sens_amp`
`x2 net2 IN[1] VREF sens_amp`
`x3 net1 IN[0] VREF sens_amp`
`x4 OUT[2] net3 adc_bridge`
`x5 OUT[1] net2 adc_bridge`
`x6 OUT[0] net1 adc_bridge`


`.subckt sens_amp  OUT V_IN REF`
`*hidden`
`.ends`

`.subckt adc_bridge  D_OUT ANALOG_IN`
`*.ipin ANALOG_IN`
`*.opin D_OUT`
`abridge [ANALOG_IN] [D_OUT] adc_buff`
`.model adc_buff adc_bridge(in_low=0.9 in_high=0.9)`
`.ends`
`.GLOBAL GND`
`.end`

1.png

<@U02NGKNUN5V> see xschem example (do not run under any sky130 project directory)  logic/test_ngspice.sch

<@U02NGKNUN5V> I also had problems with bussed signals (OUT[2] and similar), the solution was to add a '`netlist_options.sym`' component with following attribute:
`bus_replacement_char="xx"`
Above attribute means: replace `[` with `x` and replace `]` with `x`.
So in your saved raw file the OUT[2] will be saved as OUTx2x

<@U02NGKNUN5V> the '[ ]' characters have different meanings for ngspice and xschem so i had to replace them. May be there is a better replacement instead of 'x x', you may experiment...