You have uploaded a verilog-a patch but most people dont know how to perform a patch. So kindly upload the full verilog-a file rather than just the patch. I mostly struggled with the xyce and xschem integration. Other than that I think that the example is sufficient. If you can however create a readme file containing all the steps to perform this simulation it would be helpful to a lot of people. I can do that if you would like me to do.
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Barak Hoffer
07/27/2022, 11:48 AM
Just to clarify, the xschem example is also in the repository. I will add a readme. Thanks
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Binoy B
08/02/2022, 10:48 AM
Is there a spice model for reram?
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Talha Bin Azmat
08/03/2022, 4:10 AM
Umm no. There is a verilog a model for the memristor. So you have to use verilog-a model to simulate the reram using xyce