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Please assist me in determining whether this circu...
# analog-design
r
Please assist me in determining whether this circuit operates as a monostable and how to obtain square wave output if it does.
a
that is definitely not a monostable
l
What is your testbench? What is the input of your circuit? The load? Why do you have a resistor ladder with about 1 mA consumption?
r
@Luis Henrique Rodovalho The one mentioned circuit I have use as symbol input as DAC for now just trying to test with voltage source PWL output I left open for now to check R1 and c as RC network R2 and R3 Voltage divider I am not able figure out what value resistors and capacitor should be used from xschem device library 🤔.
l
You need some kind of feedback and trigger to make monostable circuits. Your output is just computing error, as it seems. It doesn't have a load. You should show us your testbench.
r
@Luis Henrique Rodovalho Hello , i was attempting to do this, but now i am trying to determine the correct approach.
@Luis Henrique Rodovalho i have tried this also .
l
The first circuit would never work because there is nothing connected to the output. The second also would never work because the input is connected to a resistor connected to ground.
r
@Luis Henrique Rodovalho For the output, I was just trying to test. In that case, should I connect something and test? Should I also remove the resistor and ground connection at the input? will that be enough to work as monostable resistor i have used are gen.
l
You're thinking too much about resistors. Resistors are good for discrete circuits, but it is not the power of microelectronics, where you can place several transistors in a tiny place.
You could try to make a circuit with the 555, as you intended in the beginning. There are even some fully functional models for it that could work with xschem and ngspice. Maybe you could port its functionality to Sky130 process and even tapeout it.
r
Thank you so much for your guidance .
l
Try to design this relaxation oscillator here.
r
Thank you
@Luis Henrique Rodovalho Hello sir, I need a suggestion. In my plan, we have made some changes and are now using an external clock instead of a DLL or PLL. How can I gain control over the number of pulses? Can I use a counter comparator? Do you have any resources on this topic please?
l
Make a Johnson counter. Use nor logic gates between the phases to get your duty cycle. The speed is limited by the flip flop maximum frequency.
r
Thank you so much
i was trying to just test this was the outcome. there is a jitter
@Luis Henrique Rodovalho i tried to provide two pulses of specific width as a clock, but the output is not matching the input.
l
The last ff output must be inverted
r
Thank you sir
@Luis Henrique Rodovalho Still there is a jitter and output values got inverted i mean values of the output is in negative i want try replicating the clock values in output
This are the two simulations from clock(external clock ) with high width but output is completely reducing it and making it multiple pulses
l
I don't have the slightest idea of what you are doing. This circuit is a frequency divider. Does the circuit work? Is the frequency of the output a fraction of the input?
In my opinion, you should try even more basic circuits. Try to make a simple divide by two frequency divider. If it works, go to the johnson ring. Some of your curves seem like a gated oscillator. But, in the end, I just don't know what are you doing.
You need to get this
r
I want to have control over the pulses when an external clock is given to the digital controller with different frequencies for different operations. I didn't mean to create a frequency divider - I am sorry if i misunderstood to follow your guidance.
i want to just copy the the pulses in the output but having the control over number of pulses
l
See. In this timing diagram, you have four phases. After that, you can use logic to make output with 4 times less frequency. But you can control the duty cycle, so you can have a signal with 25% or 75% duty cycle, for example
If you have ten phases, you could have a duty cycle of 10% steps
For example. You could have a 1 MHz input clock and a 100 khz output signal with programmable duty cycle
But first you need to at least make your frequency divider.
r
but i am allowed to use external clock so i was thinking to have the changes from outside only lets say when i need the bunch of pulses with ns according to that frequency pulse i will give and use it i thought
l
This is the least efficient way to have a programmable duty cycle, and the easiest one.
r
yeah i understand now sir thank you but in my project variable external clock is allowed because of that i am confused
l
Ok. Later I will give you some working examples.
r
thank you so much
l
What is you FF circuit? What is connected to the clear input?
r
I just thought to test the idea so I just used DFF where clock is considered as external pulse. I didn't use clear in it . First to test I thought later if it works I can make proper with clear I thought @Luis Henrique Rodovalho
l
You should test your DFF first.
r
Okay I will test it and check DFF. What if we use AND gate 1 input as clock other as enable signal as 1 I am not sure what will happen.
DFF TEST RESULT @Luis Henrique Rodovalho
l
It's clearly oscillating. Try to test your DFF as a div by 2 with feedback, not with independent data and clock signals.
r
okay i will test thank you
l
Your Johnson counter looks like a gated oscillator. It could happen if you're using latches instead of flip flops. When you enable the clock signals, it is turning into a ring oscillator. You are not getting the outputs expected in the timing diagram.
r
this is the circuit of my DFF
to test DFF as div by 2 with feedback do you mean to have 2dff as Johnson counter instead of having 4
l
You have a latch, not a flip flop. You can make a master slave flip flop using this as a template. With this latch, your circuit won't work.
r
ok thank you
l
Screenshot_2024-06-29-11-23-32-199_com.opera.browser-edit.jpg
This is a very slow edge triggered flip flop. This topology is not used in the industry. It's for didactic reasons only.
This is a better flip flop, the C2MOS
r
Okay, sir. Thank you. I guess this will help me achieve faster pulses for a better flip-flop. I have to add a reset option as well. I was testing that earlier with DFF.
@Luis Henrique Rodovalho Thank you so much sir now its almost working but the output pulse is going negative for low its following the pattern and width but for low is negative and how can i put reset in that? could you please let me know thank you
l
It is not working. Check the voltages.
r
I had a wire connection issue which I fixed. After that, I got an output with a different voltage but the same width of pulses. Following this pattern of pulses, I'm planning to use a DAC to change the amplitude. I think it should be okay in that case, right? The output doesn't touch the zero scale for low pattern when compared to the input clock. I had to add the reset option in the circuit, how can I do that? could you please let me know @Luis Henrique Rodovalho
Screenshot 2024-06-29 075145.png
l
It is still not working. The output voltages are worng. The best way to test your flip flop is with a divide by two.
r
okay i will try that
after testing with divide by 2 i can see voltage drop in output @Luis Henrique Rodovalho
l
Because something is wrong. It can be the testbench.
r
okay i will look into and this is my test bench
l
This is the divide by 2.
r
ohh sorry thank you after making this circuit i am not having qbar terminal in symbol so i am adding inverter symbol while using the mentioned FF symbol
l
No problem. Try to modify your symbols. Your inverter one is really bad. Try to put the inputs at the left side and the outputs at the right one. Your schematics are becoming too confusing.
r
okay sir thank you
This is the output for divide by 2
l
Nope.
r
that means something to do with fliflop
@Luis Henrique Rodovalho i got the output now but its following supply voltage 1.8 when i have given clock voltage as 1.5
l
Why are you using a 1.5 V clock signal and 1.8 V? You should never do that with regular CMOS logic!
r
ohk i wil try with 0.9v
thank you
l
No! 1.8 V!
r
ohk thank you so much i understood now the whole process now i am just left to add reset option sorry and thank you so much for giving your time to help me sir
l
Here goes a working Johnson ring.
fdiv.zip
r
@Luis Henrique Rodovalho Thank you so much, sir. I have checked its working as expected. To add a RESET option, I have added an NMOS at the output of Q DFF. Is this the correct way to add the reset option?
l
It isn't the correct way, and the reset input is not needed for this circuit to work. The reset input must be inserted someway inside the tri-state inverters, otherwise, you can have a short circuit inside your FF.
r
this was the output using that option vout was having the high signal in begninng same as the vrst so i thout to add inverter one more which output is Vpwm anyways this is wrong as you mentioned i will try looking reset option i need this option in the reset if use the clock with different frequency or to make a single pulse i need to reset it . @Luis Henrique Rodovalho
l
I was inspecting that FF circuit I sent you, and the output signals seem to be inverted.
This is the DFF I'm using
r
Yes, I am sorry to have caused confusion earlier. I was just seeking clarity regarding the reset option by showing my earlier work
l
image.png,DPFFs.pdf
r
Thank you so much
@Luis Henrique Rodovalho Hello I made a significant connection mistake earlier, which I mentioned in the first picture. After simulating the provided circuit, I discovered that the output waveform has a significant delay between every pulse in the NOR output. Initially, I thought the output was as expected, but it turns out it's not. example:What I actually need using the external clock, which has a 10ns width with continuous pulses, to be used for the following operation: - The first operation requires 8 pulses, then a reset. - For the second operation, I need 1 pulse, then a reset, followed by a different frequency clock, with a 20ns pulse reset, 20ns pulse, and so on then reset whole. could you please suggest about it. Thank you
l
The input of the johnson ring can be controlled by using a mux, so you can switch from a 100 MHz frequency input to a 50 MHz. You can have a frequency divider for it. Anyway, first you must finish your pulse width modulator, and you will need muxes for it. There is a delay for the nor outputs, and you can always resync them with flip flops.
r
Thank you @Luis Henrique Rodovalho FOR PULSE MODULATION I AM DOING WITH EXTERNAL CLOCK so i will have continuous pulses now trying get control over the pulse count without delay in between
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