Thinking of renting some CPUs and generating lookup tables for a ton of amplifier circuits. Does this seem worthwhile? What could go wrong? (not sure who to @. Maybe @Tim Edwards @Boris Murmann ) • Amps: Common gate,drain,source, diff pairs, cascode amps, etc etc. With & without feedback. Probably just voltage-voltage amps. • Metrics: Record offset, gain, bandwidth, linearity, poles, phase margin, CMRR, PSRR, noise, slew rate. Area obviously. Sensitivity of all of those to mismatch & temperature & corners. • Variations: 1.8V and 3.3V power supplies. pfet and nfet. lvt, hvt, and other transistors. Different kinds of resistors. etc etc. • Presentation: put it in postgres and csv and pandas and let people download the file. Maybe also put up a little webpage where you can query with sql too and make plots. • Value proposition: Bob wants an amp with low gain and low offset and low area and doesn't mind noise. He can query the db and find one. • idk anything about gm/id methodology or how that would tie in.

My main concern is that the design space is too large.

Which tons of amplifiers are you talking about?

I was thinking maybe the amps in chapter 3 of Carusone & Johns & Martin

The problem is that the testbenches must be standardized. Also, complexity differences can lead to different layouts and the performance can be misleading.

How misleading are we talking? What if I added some arbitrary resistance & capacitance to every wire? Not good enough -- need realistic values?

I tried some time ago to compare basic topologies of frequency compensation using minimum size transistors. It is a start. It's good for learning purposes.

You'd bet the giant table at the end wouldn't be super useful though?

Try something easier first, like current mirror topologies, or buffer stages. I think there are notebooks for that kind of thing.

Notebooks?

How would one use the lookup tables that you'll generate from this exercise? (I'm looking at your value proposition... are you thinking it will be like an "opamp selector" when you go to ti.com or analog.com?)

https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-design-contest/ Jupyter Notebooks

> How would one use the lookup tables that you'll generate from this exercise? (I'm looking at your value proposition... are you thinking it will be like an "opamp selector" when you go to ti.com or analog.com?)

SELECT * FROM differential_voltage_amps WHERE total_area < 100 AND open_loop_gain > 100 AND mismatch_offset_std < .001

Get back spice netlists i guess. The netlist would have a tag saying which circuit it is (eg fig1) and you could look at the picture. Could filter to a certain circuit in the sql too. I've never used those tools. will check them out.

I see. As Boris mentioned, the design/parameter space is really large. You're not only searching over device sizes but also topologies. If I want mismatch_offset_std < x, I can size devices (sizing), or I can use autozeroing, or I can use chopping (topology). It's a hard problem!

Hey searching over topologies is a small constant factor. Yeah maybe using a brain and Actual Techniques is better than a giant table.... hmm

As a designer, I don't mind thinking about device sizing and topology choices. This is actually the fun and rewarding part. But I would LOVE to have automation to help speed up the tedious parts of the work (like layout...)

In my head automatic layout is easy but looking at the market github graveyard, it is a very very hard thing. I am a newb still as my username says.

https://github.com/lhrodovalho/sky130_rodovalho_ip__amp Try it. It is a start

As a designer, I don't mind thinking about device sizing and topology choices. This is actually the fun and rewarding part.

This is surprising to me. I thought deciding topology and sizes and bias currents took 1000 years and is a giant pain in the butt. Just because I'm a newb? The pros breeze through it?

The simple topologies are ok. The problem is that most of them shouldn't be used in real silicon. And, in the end, what is really difficult is the specifications. That is why I admire the system guys. There is a huge difference between a working amplifier and an useful one that doesn't waste resources. Without an application, a circuit specification is nothing. It is arbitrary.

I wouldn't say anyone breezes through it, but I would spend time talking to designers (or spend time getting familiar with it) to understand what the biggest obstacles are. Also, it's OK to disagree with me 🙂 You can develop these things and if people find them useful, they'll get adopted!

Here I have 9 testbenches for a single intermediary opamp topology: https://github.com/lhrodovalho/sky130_rodovalho_ip__lpopamp Here I have 5 basic topologies and just one kind of testbench, a AC one: https://github.com/lhrodovalho/sky130_rodovalho_ip__amp/ If you can, you could adapt those 9 testbenches for those 5 topologies and compare them. Maybe even write some documentation, as it doesn't have any. Then you can think about comparisons. And they are just 5 basic topologies!

I'll take a contrarian position to Luis on the usefulness of amplifiers without an application. (Not to say that I'm right but just to offer an alternative) There are ~4 kinds of metal hand saw in most workshops and they serve virtually every application known to man. Not perfectly but well enough. They are a tool. If you look at FPGAs and MCUs there are less than a dozen common amplifiers in use on about 90% of them. While thousands of application specific optimizations could be made for unique applications, the vast majority of real world problems {more than 90%} can be solved with a relatively small/manageable suite of amplifiers topologies surrounded with appropriate feedback structures. If you want to serve the entire universe of analog design the range of tools {amplifiers} required is far more broad. This is obviously not a binary discussion an the reality is that many different blends of standardization and customization have value for different consumers of the amplifiers.

Well, Andrew, I agree with you. In ASICs, if the simple topology works, it is used, even if it is not the best performance wise. Even in the state-of-art technologies with single digit nanometer gate all around transistors, you will find resistor based constant gm current sources biasing a single stage differential pair. For the simple reason that, if you have something complex, inexperienced circuit and layout designers can mess it when porting them to new projects. However, I just refuse to believe that the engineers at Analog Devices and Texas Instruments use simple topologies for discrete general purpose operational amplifiers they sell.

Yeah, I mean, just look at the 741, and thats a simple old one. My big problem once upon a time was that while we did a lot of simple stuff linked together - lot of cascode, etc, but the models were always rubbish until we got parasitic extraction, so we got into kinda a weird design loop for stuff like the VCO and charge pump. Although this was PD-SOI, so the models were extra terrible.

Luis, We should ask them....They won't be able to talk about current products but I'm sure that some deisgns from say ~20yrs ago would be fair game and would be very helpful for the community to understand the gap from concept and academia to world leading products.

Do we have some of them lurking here?