Hello, I'm trying to run an LVS with a Verilog file in the precheck without success. I designed a D flip-flop using OpenLane and I want to test only the LVS. I have tried many things with or without a wrapper/analog wrapper, and with or without a netlist. In fact, I don’t know how to properly run an LVS with a Verilog file. This step is important to understand how it works before designing a larger circuit. If someone could help me, it would be great. Thanks!

@Charly Meyer LVS with precheck is all controlled by the

lvs/<cell>/lvs_config.json

file. You can also just run LVS with the

make lvs-<cell>

target if there is a

lvs/<cell>/lvs_config.json

file. Verilog generally has references to standard cell libraries, so be sure to include those. Here’s the standard

lvs_config.json

file for

user_project_wrapper

.

{
  "STD_CELL_LIBRARY": "sky130_fd_sc_hd",
  "INCLUDE_CONFIGS": [
    "$LVS_ROOT/tech/$PDK/lvs_config.base.json"
  ],
  "TOP_SOURCE": "user_project_wrapper",
  "TOP_LAYOUT": "$TOP_SOURCE",
  "EXTRACT_FLATGLOB": [
    ""
  ],
  "EXTRACT_ABSTRACT": [
    ""
  ],
  "LVS_FLATTEN": [
    ""
  ],
  "LVS_NOFLATTEN": [
    ""
  ],
  "LVS_IGNORE": [
    ""
  ],
  "LVS_SPICE_FILES": [
    ""
  ],
  "LVS_VERILOG_FILES": [
    "$UPRJ_ROOT/verilog/gl/user_proj_example.v",
    "$UPRJ_ROOT/verilog/gl/user_project_wrapper.v"
  ],
  "LAYOUT_FILE": "$UPRJ_ROOT/gds/user_project_wrapper.gds"
}

Thanks for your response. Sory, I need to be more accurate in describing my problem. I'm wondering if there is anything else to do (except filling the lvs_config.json file). On the console, the LVS fails, but the lvs.log says, "Final result: Circuits match uniquely." I don't know what to think about that.