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Is it possible the resistance extraction is a bit pessimistic ? I'm doing a power gate and the Ron ...
# magic
t
Is it possible the resistance extraction is a bit pessimistic ? I'm doing a power gate and the Ron of pex is about 50% higher than in sim. When checking, the Ron of the fingers of the power pfet (voltage drop across them) is pretty much what I expect, but then the resistance to go from those fingers to the met4 large pins is much higher than I expect (like a good 5 times higher than even my "worst case" manual estimates looking at number of vias and trace width/length and such).
m
@tnt are you asking about the precision of magic parasitic resistance extraction? There’s a disclaimer on the pex page here. See the Resistance sub-section.
t
Well I'm using 
extresist
😅
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# Run extraction
extract path ext
extract all

ext2sim labels on
ext2sim -p ext

extresist tolerance 10
extresist

ext2spice lvs
ext2spice cthresh 0.01
ext2spice extresist on
ext2spice -p ext -o $project.pex.spice
m
Right, here’s the disclaimer I was referring to
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This approximation for resistance does not take into account any branching, so it can be significantly in error for nodes that have side branches. Figure 2 gives an example. For global signal trees such as clocks or power, Magic's estimate of resistance will likely be several times higher than the actual resistance between two points.
t
(wish there was a online preview 😅 )
a
I've got a suspicion on this one. Which transistor in the picture are you referring to?
Do you have any parsing of the network resistance you get in the extracted netlist?
t
@Mitch Bailey: That disclaimer does not correspond to "extresist". It corresponds to the resistance extraction that is enabled if you do "ext2spice rthresh <something>", which is a "lumped resistance" approximation that is understood by exactly zero tools in the flow.
@tnt: I fully expect the resistance extraction to be pretty close to the actual value. What are you expecting for the resistance through the contacts between diffusion and local interconnect? It is very high at (nominally) 585 ohms per contact for p-diffusion.
(Note that using the high side corner for resistance, the p-diffusion contacts are 840 ohms per square.)
m
@Tim Edwards thanks for the correction! I’ll attempt to make amends in my previous posts.
t
@Andrew Wright The giant large pmos 🙂 nf=244 and W=7.25u per finger.
@Tim Edwards I indeed didn't expect the licon contact to be that high. I have a lot of them ( 2500 for the source and another 2500 for the drain ) but still, that's about 0.45 ohm right there. I simulate 2.1 ohm from design schematic and get 3.1 ohm after PEX. But the rest is probably explained by the fact the ports are defined as the whole high of the transistor ( which is almost 100 u tall ! ) because I know that those will end up connected to several 
met5
rails of the PDN and so it's distributed across but looking at the pex log it seems magic put the drive point at one of the edge.
FWIW, I now simulated by also including the rails connecting to the large pads. So I'm feeding current in and out at each intersection point and now the results are more in line with what I expected. So my issue was because I had a very tall pad/port/label that in the real circuit I feed in a distributed fashion at several point along its length, but when it gets extracted as a single port, the single feedpoint introduces a fairly large error, so I need to extract the proper feedpoints.
t
I find it very hard to figure out in any obvious deterministic way how to do the parasitic resistance network extraction at the terminal of a device. The device model only has one point of contact, so the model itself will never be able to model the complexities of the layout except maybe by splitting the layout device into multiple components, which has another whole set of issues. . .
t
No, I understand there is no good way to do that and I think me having to narrow down the feed points into several ports is the only way to deal with that.
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