Hi all, LTC2 gds has

IO.0

drc errors on COMP that already have

Latchup_MK

over it. How to fix that error?

1. To flag I/O latch-up related violation:
    (a) Non well tap COMP directly connected to PAD is recommended to be marked by "Latchup_MK" layer
    (b) Min/max Latchup_MK layer overlap of COMP (directly connected to Pad) LV=0 MV=0

@aquiles viza Is this related to this previous discussion? If it is, the device may be too big to pass the

IO.0

rule. Maybe a screen shot and explanation would be enough for CMC/GF to waive this DRC error. https://open-source-silicon.slack.com/archives/C04MJUYP99V/p1715698171145149?thread_ts=1715666213.928639&cid=C04MJUYP99V

I would say it's not related, because this error happens on another design (image1) and some of the waffle COMP despite having the

Latchup_MK

layer over them.

The first one appears to be missing a double guardring. Could that be the problem/

Yep, the first design doesn't have the guard rings, but we though those errors were indicated with other

IO

errors, not with

IO.0

.