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Hello <@U01QTMG2K8R> <@U01819B63HP> Can someone ...
# analog-design
r
Hello @Luis Henrique Rodovalho @Stefan Schippers Can someone give idea or reference how to draw the pulse generator circuit that have control over pulse width and voltage . And also how can we do using DAC ?
l
Which kind of pulse generator are you talking about? If you're designing a switched capacitor DAC, the most important feature you need is non-overlap clocks. For pulse width modulation kind of DACs, you have counters. You will need a voltage reference and buffers. It's hard to know what you should do without knowing which kind of DAC you're designing.
r
@Luis Henrique Rodovalho my main goal Is to have square wave pulse that we can do in xschem using voltage source [t v,t v..] format time voltage same thing I want to have in circuit where I can control both time in ns and voltage from 0-5 v as output for generating pulse I thought going with DAC would be easy. So do you have any idea and references?
@Luis Henrique Rodovalho
l
You could try a RDAC for voltage and level shifter controlled by a reference clock where the supply is a buffered version of the RDAC output.
I just don't know why you need this chopped output, where the signal returns to ground.
r
@Luis Henrique Rodovalho thank you I was trying to use for reram memristor. That will help me to draw the schematic circuit to generate pulse with having control over pulse width and voltage? Do you any reference for this ?
l
Not right now. Just look for PWM and RDACs.
r
Okay thank you.
l
be warned there's kind of a reram memristor graveyard. I asked a couple people who did it on MPWs if their chips worked out and they said they had issues, but I didn't ask details. I think the spice models are somewhat incomplete or something.
r
@Luke Harold Miles thank you for the info .
l
Here's an xschem port of an array design we did with SkyWater RRAM back in 2021. Verification tb's are a work in progress, but I can give you a copy of much of the controller RTL if need be: https://github.com/lupto/ytv-opensource (Some schematics in https://ieeexplore.ieee.org/document/10129298) We did pulse height and width control for a successive project. Height control was with a 5-8 bit RDAC and LDO for BL/SL and WL accordingly. Pulse width was controlled by a fsm: https://ieeexplore.ieee.org/document/10504791 RTL: https://github.com/akashlevy/ember-digital
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r
@Luke Harold Miles thank you so much.
@Luis Henrique Rodovalho Hello I am considering using a PLL to set the frequency, a DAC to adjust the pulse amplitude, and two 555 timers as clocks. One 555 timer would be in astable mode to generate square waves, and the other would be in monostable mode to control the width of the pulse. The width of the pulse in the astable mode would be adjusted using the DAC for changing the width, which would be the input to the monostable 555 timer. astable 555 timer gets input from monostable 555 timer monostable 555 timer will get from the DAC total 2 dac,2clocks,PLL i am planning to use Could you share your thoughts on this setup or suggest any improvements please?
l
Could you do just one astable timer and digital counter circuit (or frequency divider) to modify the pulse width you intend to feed to subsequent blocks?
r
In one stable timer I'm not able to change the pulse width without any external clock astable requires to change the resistor b So my idea was to use one Short learning through monostable timer that can change the width through DAC.
l
Could you use the single astable timer to generate a frequency that you can then base your other clocks/pulses off of? So this 555 would give you the fastest frequency your chip could operate at and then you could divide it to get the frequency you need for subsystems. We didn't generate the clock on-chip for our RRAM macro, but we took a central digital clock and used counters/dividers to get our write pulse widths and sense amplifier clocks.
r
Okay thank you so much for helping.
l
https://electronics.stackexchange.com/questions/165552/rising-edge-pulse-detector-from-logic-gates You can generate short pulses with this circuit. It is easier to do than a 555. You just need to control the inverter delay. You can do that with tri-state inverters, for example. https://www.sciencedirect.com/science/article/abs/pii/S0026269219305580
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I think DLLs are easier to design than PLLs, if you just want a 100 MHz clock, as you use in your example. A PLL is just fine, anyway. The key aspect is specifications. How precise does your reference period need to be? And the clock width? The 555 is an interesting and versatile circuit, but it is an general purpose discrete integrated circuit. If you can design you own circuits, all in one, it is not the best choice.
r
For SET, pulse timing can be very short (~10ns) as long as voltage is high enough (e.g., 2V). For RESET, pulse timing is usually longer (~10us) for reasonable voltage (3.3V). For FORM, you often need 1-10ms pulses
l
@Rafeeq Khan Mohammed if your main concern is the RRAM write pulse width, having some jitter in the pulse isn't too much of an issue. Variations in the pulse amplitude typically have a more pronounced effect than the width.
r
also i want to use pulses for reading @Luke Harold Miles
l
That could be more challenging depending on 1) your BL/SL capacitance, 2) the read resistance range you want to use for your cells, and 3) your target read frequency. Basically it boils down to how close your target clock period is to the worst-case signal settling time you expect during read.
r
ohk than i have to look for that thank you.
@Luis Henrique Rodovalho how can i have precise controlling for delay using tri state inverter i am confused could you please help me to know
@Luis Henrique Rodovalho with tri state inverter I guess I will not be able do deal with all the scale ns ,microsec, and millisec Can I have clock of kHz in DLL for millisec If I would have also it will be difficult to go back to ns pulse micro and millisec If I want to generate that big clock I have to have VCO. I guess PLL would be better in that case Could you please share your thoughts on this.
l
You can mix a DLL with a pulse generator to generate an pulse with programmable width
r
@Luis Henrique Rodovalho thank you
@Luis Henrique Rodovalho To generate the delay and combine the edges to create a high-frequency clock output, I think a large number of inverters will be required.? :time scale for ns,micro sec and ms
l
The number of stages is related to the precision of your duty cycle. If you have N inverters, you could make a logic from a duty cycle, you can have duty cycle in steps of 100%/N. The period of the reference clock should be something like N times the inverter delay. The inverter delay is a function of its supply voltage, which can be controlled in several ways. I think you can have delays ranging from ms and ns with the open source technologies.
r
@Luis Henrique Rodovalho thank you sir
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