@Tim Edwards can you confirm? From the user_project_wrapper perspective, it looks like the logic analyzer interface consists of 3 buses: 2 inputs

la_data_in

and

la_data_oenb

and one output

la_data_out

. The

la_data_oenb

is asserted (active low) when the corresponding

la_data_in

signal is valid and high otherwise. Does this mean that the

la_data_in

signal should not be used when

la_data_oenb

is high?