Hello everyone here, I am newbie using the open source tool OPEN-ROAD for RTL TO GDS||. While reading the Netlist generated from the yosys it throws syntax error also when i am trying to read design file. It also throws the same error. Can anyone guide me how to fix this. I have simulated the code on other tool and has no error.

@Rahil Vahora Can you share your verilog file(s)?

Yeah sure

Maybe the #openroad channel would be a good place to ask.

Do you know any openroad channel