Hey, we are trying to make tapeout deadlines but we are having issues with hold time violations. We are having timing closure on our top macro, but not on user_project_wrapper (which just hooks up the ports to the

mprj

macro). Do you have recommendations on how to approach this? It looks like the top-level user_project_wrapper don't insert buffers during synthesis, do we need to change some configuration variables to allow that, and is this safe?

@Edmund Lam I believe that other users have experienced the same problem. I think there may be 2 solutions. 1. make the timing constraints on your hard macro more conservative. 2. convert your top macro to a soft macro and synthesize the top level. Here’s a sample

user_project_wrapper/config.tcl

for top level synthesis.

{
  "DESIGN_NAME": "user_project_wrapper",
  "VERILOG_FILES": [
    "dir::../../verilog/rtl/defines.v",
    "dir::../../verilog/rtl/user_defines.v",
    "dir::../../verilog/rtl/user_proj_example.v",
    "dir::../../verilog/rtl/user_project_wrapper.v"
  ],
  "CLOCK_PERIOD": 25,
  "CLOCK_PORT": "wb_clk_i",
  "CLOCK_NET": "mprj.clk",
  "PL_TARGET_DENSITY": 0.3,
  "GPL_CELL_PADDING": 2,
  "DPL_CELL_PADDING": 1,
  "GRT_ADJUSTMENT": 0.2,
  "MAGIC_DEF_LABELS": 0,
  "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
  "IO_SYNC": 0,
  "MAX_TRANSITION_CONSTRAINT": 1.5,
  "FP_PDN_VPITCH": 180,
  "FP_PDN_HPITCH": 180,
  "FP_PDN_VOFFSET": 5,
  "FP_PDN_HOFFSET": 5,
  "MAGIC_ZEROIZE_ORIGIN": 0,
  "FP_SIZING": "absolute",
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "RUN_CVC": 0,
  "UNIT": 2.4,
  "FP_IO_VEXTEND": "expr::2 * $UNIT",
  "FP_IO_HEXTEND": "expr::2 * $UNIT",
  "FP_IO_VLENGTH": "expr::$UNIT",
  "FP_IO_HLENGTH": "expr::$UNIT",
  "FP_IO_VTHICKNESS_MULT": 4,
  "FP_IO_HTHICKNESS_MULT": 4,
  "FP_PDN_CORE_RING": 1,
  "FP_PDN_CORE_RING_VWIDTH": 3.1,
  "FP_PDN_CORE_RING_HWIDTH": 3.1,
  "FP_PDN_CORE_RING_VOFFSET": 12.45,
  "FP_PDN_CORE_RING_HOFFSET": 12.45,
  "FP_PDN_CORE_RING_VSPACING": 1.7,
  "RUN_HEURISTIC_DIODE_INSERTION": 1,
  "HEURISTIC_ANTENNA_THRESHOLD": 110,
  "GRT_REPAIR_ANTENNAS": 1,
  "FP_PDN_CORE_RING_HSPACING": 1.7,
  "FP_PDN_VWIDTH": 3.1,
  "FP_PDN_HWIDTH": 3.1,
  "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
  "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
  "VDD_NETS": [
    "vccd1",
    "vccd2",
    "vdda1",
    "vdda2"
  ],
  "GND_NETS": [
    "vssd1",
    "vssd2",
    "vssa1",
    "vssa2"
  ],
  "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
  "pdk::sky130*": {
    "RT_MAX_LAYER": "met4",
    "DIE_AREA": "0 0 2920 3520",
    "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 25
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "SYNTH_MAX_FANOUT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcuC": {
    "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "FP_PDN_CHECK_NODES": 0,
    "FP_PDN_ENABLE_RAILS": 0,
    "RT_MAX_LAYER": "Metal4",
    "DIE_AREA": "0 0 3000 3000",
    "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
    "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
    "DIODE_INSERTION_STRATEGY": 0,
    "MAGIC_WRITE_FULL_LEF": 0
  }
}

You may have to adjust these parameters (and others to pass timing)

"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
    "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,
    "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.2,
    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,

Maybe

SYNTH_STRAGETY

too.

Thank you so much! As an update, we managed to get things to work using IO_PCT on the macro instead.