Hi Everyone, I was searching for the current best practices for using digital blocks in the analog wrapper here on Slack channel history and could not find a clear answer. What is the best way to integrate a digital block inside the

user_analog_project_wrapper

? Is it by synthesizing the block in openlane and doing the routing "manually" using magic? I found some people asking the same, but no good answer: is it possible to route in

user_analog_project_wrapper

similarly to what is done in the digital flow and the

user_project_wrapper

? The idea of just porting and tweaking the config files between wrappers work?

@Rodrigo Wuerdig Not sure what the best practice is, but it has been done. Things you’ll need to keep in mind. 1. The

caravel_user_project_analog/openlane/Makefile

may be a bad link. I’m pretty sure you can delete it and user

caravel_user_project/openlane/Makefile

. This is the makefile that actually calls openlane and is imported in

caravel_user_project_analog/Makefile

. 2. Calling a verilog block from the analog spice can be tricky. If you’re using xschem, you’ll need to create a symbol with the pins in the verilog port order. You can either use the

sim_pinnumber

property, or manually edit the symbol file to put the pins in the order you want. Set this property on the symbol

type=primitive

. 3. For LVS, you’ll need to read both spice and verilog netlists which can be specified in the

lvs/<block>/lvs_config.json

file. See examples in

mpw_precheck/checks/be_checks/tech/sky130?/lvs_config.*.json

. This LVS will run with

make lvs-<block>

if you use the

caravel_user_project/Makefile

. I don’t think

caravel_user_project_analog/Makefile

has this target yet. 4. I don’t think the analog flow has timing checks, so be aware of that.

Thanks a lot, David! That is a good north