Hi all, I'm working on understanding the flow of synthesis, using OpenROAD and the using KLayout using OFRS. I've taken the YoSyssynthesis output from https://github.com/OuDret/OnlyNandYosysSynth/tree/main/OnlyNandYosysSynth/output and am trying to smoke tests one of the gate-level netlist results using this guide in the picture below. However, I continually get errors like this. May I know if running flows on really simple designs like this requires more than just the gate-level netlist Verilog file or can the flow just run using it the gate-level netlist produced by YoSys? I'm super new to this and help would be greatly appreciated.

Its says missing module reference

jpeg_rle

. Include all modules as per top design