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Hello everyone. I'm working on the design of a r...
# analog-design
e
Hello everyone. I'm working on the design of a recycling folded cascode OTA. I've met my gain and bandwidth specifications of >80dB and approx. 300MHz. But there's an issue with the phase margin(plot). In fact, towards the GBW frequency in the phase plot the graph looks unusual. Please any insight on this will be greatly appreciated. @Luis Henrique Rodovalho @Tim Edwards @Mitch Bailey @Luke Harold Miles @Stefan Schippers
u
In your plot, phase is wrapped around after -180 degrees. The phase at GBW is -240.
e
Thank you. But I want to know what may have caused it. I thought it would have been because the GBW is closed to the second pole which is bounded by FT, intrinsic unity gain frequency. But from my calculation the FT of the device technology is in unit of GHz. The formula I used for the calculation of the FT is attached with this message.
u
You are right, your second pole is close to GBW. Your assumption about the second pole is not right. Analyze nodes vx and vout.
s
Looks like at low frequencies your loop gain is positive instead of negative(that is, phase=0 instead of 180). So may be your AC source or something else is reversed. In general you want a negative feedback, that means, at low frequencies you have high gain and 180deg phase shift (negative loop gain).
r
Looks like you have more than two poles, hence the extra phase shift before unity loop gain, so you're not going to be stable. Look for parasitic capacitances connected to high impedance nodes and try to characterize their time constants to tell which ones are most important. You may have to tweak your design to kill gain at higher frequencies for certain nodes to add zeros to the transfer function and stave off instability. This sort of compensation is pretty standard since otherwise your parasitics eat your lunch
I would ordinarily recommend a dominant pole compensation approach because it's the easiest, but you're going for a pretty fast design so that might not be acceptable. Maybe try a lead compensation style like that described here: https://www.d.umn.edu/~htang/ECE5211_doc_files/ECE5211_files/Chapter6_part1.pdf or something similar
I know very little about your design, @Emmanuel Innocent, but it looks like from your screenshot above, you have some cross-coupled parallel input stages (I'm not acquainted with terminology for the topology so forgive my ignorance), but I would guess that those cross-coupled structures will have very high output impedance since they are tied to the gates of your current mirrors and whatnot. I wouldn't be surprised if the parasitic capacitance on those two nodes (one for each half of your circuit) add poles. You get the miller effect for this transistor's gate-drain capacitance, so it probably gets effectively multiplied a lot - perhaps start there?
Oh I see this is the so-called "recycling folded cascode" topology that you mentioned. I haven't heard of it before. Neat! It seems like some other folks may have been worried about the stability of the feedback loop that includes the current mirror in the recycling section - they seem to have a triode(?) biased transistor acting as a resistor in series with the gate of the mirroring transistor to kill its loop gain. Perhaps this sort of technique could also help with your topology's stability?
e
@Ryan Brandt Thank you very much for taking your time to explain. I'll check out the improvement that you suggested. I wanted to use a new kind of topology for my current project so I bumped into the recycling folded cascode topology.
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