I am working on an analog project that is pin-limi...
# caravel
v
I am working on an analog project that is pin-limited (i.e. have assigned all GPIOs above mprj_io[6]), but I still need SPI to set ~6 internal 16b registers. Would it be possible to simply tie user-project nets to the housekeeping spi interface, then use no-op commands before my 8b address & 16b data? This is assumes that the housekeeping SPI ignores all data after a no-op. I am open to other ideas!
m
@Vladimir Vesely If you don’t need the on-chip cpu in caravel, you might consider
caravel_openframe
which allows greater access to 44 gpio. You’ll need to be careful because you have to completely configure each gpio individually - it’s more complicated than the normal `caravan`/`caravel` version. I believe
<https://github.com/efabless/openframe_timer_example>
is the recommended starting repo.
v
Unfortunately, it looks like I need to have the bare pads of caravel to use 5V signals when VDDIO < 5V. If CSB is high, could the house keeping SPI pins be connected to the user project area? e.g. use mprj_io[0] as my user SPI CSB, but still use SCK, SDI, SDO. Then if its necessary to access the housekeeping, the normal CSB could be used.
m
@Vladimir Vesely I may be being a bit pedantic, but you’re referring to the bare pads (11) of
caravan
(the analog version of
caravel
), right? The analog connections to the gpio are limited to
VDDIO
because of the connections to the output drivers. If you connect 5V signals to the gpio when
VDDIO
is 3.3v, the disabled output driver pfet drain-bulk diode will be forward biased.
Even though you can’t change the defaults, you can reprogram gpio 4:0 to be user controlled through the onboard cpu. However, there are no analog connections to gpio 6:0 (or 37:36) due to wire length considerations.
v
Yes, this is a more clear formulation. With the requirement of
VDDIO
= 3.3V, to have pads that can handle 5V it is necessary to use
caravan
(I don't see this on the efabless Github. I was under the impression that it was replaced with
caravel_analog
?) No pedantry detected. Ah, so I could use the housekeeping SPI on startup (e.g. get the device ID), then reprogram pins 1-4 to be the user SPI. The pins would reset to default when power is lost. Is this summary correct?
m
For
caravan
(final chip name), clone `caravel_project_wrapper_analog`(repo name). The top user area is
user_analog_project_wrapper
. precheck and tapeout should pick up the gds file name (either
user_project_wrapper.gds
or
user_analog_project_wrapper
) and automatically determine the appropriate final chip type.
Ah, so I could use the housekeeping SPI on startup (e.g. get the device ID), then reprogram pins 1-4 to be the user SPI. The pins would reset to default when power is lost. Is this summary correct?
That is my understanding (I’ve never actually done it myself, though).
@Vladimir Vesely I believe
VDDIO
,
VDDA*
can be anywhere from 1.8V to 5V. https://caravel-harness.readthedocs.io/en/latest/maximum-ratings.html
v
Ah, good to know this terminology.
VDDIO
has a wide range, but the 3.3V maximum is requirement for interface. We don't want to level shift when interfacing with the chip, but still need some signals that go above 3.3V...thus preventing
open_padframe
.
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