Hello all. I imported the user_project_wrapper.gds to Cadence and I'm routing my analog design to the pad now. The pad are labeled as io_in, io_out, io_oeb and analog_io. Does someone know what they represent? Thank you!

@Kangni Liu For each of the 38 gpio pads accessible from user space on the caravel framework (37:0), you have the digital interface,

io_in

is a 1.8V logic signal input to

user_project_wrapper

from the gpio.

io_out

is the 1.8V output of

user_project_wrapper

to the gpio.

io_oeb

is the output enable low signal from the

user_project_wrapper

to the gpio. When

io_oeb

is high, the output from the

user_project_wrapper

is disabled and the output of the gpio is in a high impedance state. There are also

analog_io

connections to 29 of the gpio cells - these are straight connections through a 100 ohm resistor to the chip pad. However, be careful because they are offset -

analog_io[28]

connects to gpio 35 and

analog_io[0]

connects to gpio 7. That is, the first 7 and last 2 gpio cells do not have an analog connection to the

user_project_wrapper

. The gpio’s are configured by the settings in

verilog/rtl/user_defines.v

. If you set the gpio default to

GPIO_MODE_MGMT_STD_ANALOG

you still have access to the analog signal in the user area and you don’t need to connect most of the

io_out

,

io_oeb

signals. The catch is that the

io_out

and

io_oeb

signals for gpio 6:0 are buffered, so you’ll want to tie those off even if you’re not using those gpio for digital. If you don’t need digital input from the gpio, you don’t need to connect

io_in

.

Thank you so much!