Hi @Atif Khan, @Jorge Marin, @Gabriel Maranhão, @aquiles viza, and @Deni Alves. I just shared the first DRC results that I got from the foundry. The results are in the "CMC_drc-results_Run1" folder. The name is common for each design project. Please share with me via email the questions that you have. Based on the drc results of each die, there are three main concerns, which are common to the 3 designs: 1) Guarding around the die. For the UM tapeout that occured two years ago, we used the Caravel harness. The contact at the foundry is checking if it is needed or not. I will let you know as soon as I get his reply. 2) We need to include dummy fills for density-related requirements. 3) The RULECHECK IO.0_deck is desirable to be fixed.

IO.0 is documented here, solutions seems to be adding Latchup_MK layer over a COMP region. Can we get the calibre drc file with positions? I don't know how to find the errors if we don't have indications of their location.

Thanks aquiles i think it is not possible in magic i have to go to klayout to add this

Have they shared to your team the position of the drc errors?

If this layout is in GF180MCU, then GF should be adding the fill layers.

@Tim Edwards it is indeed gf180mcu layout.

I think Tim was talking about the foundry that is going to print the chips, not the pdk. I don't know if this pdk can be printed by other foundry

@aquiles viza CMC has collaboration with GF.

How you identify the COMPs that could be the cause for the errors?

Actually i have a guess i will request @Juan Sebastian Moya (it is holiday in 🇺🇸 )to provide location but number of error indicates that it is in my ESD circuit.

I just sent an email to CMC asking permission to share the calibre drc error files and if CMC can do the die-filling process. I will get back to you as soon as I receive a response.

@Juan Sebastian Moya Have they answered if you can share the drc error files? In any case, Do you have time for a meeting?

Still no response.