Hi, I am trying to run gate-level simulations on our wrapper, but the same tests that work with RTL would fail on our GL netlist. The GL test would fail even if I copy over the exact wrapper verilog files from the RTL folder into the gate-level folder. The setup would run fine, but midway through our testbench, all 38

mprj_io

pins would become X's despite us only using a couple of them as user input/outputs. The image is the VCD dump from the testbench. I have attached our wrapper file, the testbench, and the C file for setting the GL simulation up. Is this some problem with how we set up the testbench or with how we generate the gpios? We used

make gpio_defaults

as mentioned in the post above to generate caravel_core.v and the associated gpio blocks and our

user_defines.v

is also set. I included the wrapper and the testbench below.

This is a known issue, the solution to which has been found in this thread. I am unsure why the pull requests mentioned at the end have not been merged yet. https://open-source-silicon.slack.com/archives/C01EX4ATEKF/p1700081096438819

That fixed it for me, Thanks a lot!