Hi All, I have one question regarding

VDDIO

pin while using

caravan

wrapper for analog project. If my circuit is fully analog and used only

io_analog

,

gpio_analog

and

gpio_noesd

pins, do I need to provide any external voltage to VDDIO pin? Is

VDDIO

used to power ESD circuits under pads? Moreover the operating range of VDD for my circuit is 3V - 5V. Will 5V is too high for VDDIO pin (if it needs supply connection)? Next, I am keeping all my pins in

GPIO_MODE_MGMT_STD_ANALOG

mode in

user_defines.v

file. I do not have any 1.8V power signal in my circuit. Is it ok if I connect

io_out

and

io_oeb

to 3 to 5V signal to remove the leakage through buffers? Thank you.

@naina singhal I’m not sure about whether or not you need to connect

VDDIO

, but my guess would be yes. As far as connecting

io_out

and

io_oeb

to 3-5V power, I wouldn’t recommend doing that. Those are input to thin-ox devices and may short out if connected to voltages higher than the recommend (1.8-2.2V?).

Ok @Mitch Bailey. But I do not have any 1.8 V to 2.2 V signal in my circuit. Is there any other way to connect these

io_out

and

io_oeb

signals? Can I connect them to ground to remove leakage?

Yes, any ground would be fine.

Ok. Thank you @Mitch Bailey. Is there any schematic diagram available for these buffers if possible? I just want to have a look.

Unfortunately, no schematics. You can look at the gate level verilog for caravel_core. Find the

user_project_wrapper

instance and verify that the

user_io_oeb[*]

signals are the

io_oeb

outputs of the wrapper. You can then trace

user_io_oeb[0]

to this buffer.

sky130_fd_sc_hd__buf_6 wire2112 (.A(\user_io_oeb[0] ),
    .VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd),
    .X(net2112));

Ok. Thank you so much @Mitch Bailey.🙂

@naina singhal you can look at the gpiov2 schematic here. There are other pad cells used in the io ring, though.

@Mitch Bailey, @Tim Edwards I tried following the gpiov2.sch to understand the pin configuration but I am unable to understand most of the blocks. Can you please tell me if vddio needs to be provided externally. will a VDD range of 3V to 5V be ok for any cells connected to that pin? Sorry to disturb you guys again but I am taping out my chip on 3rd June shuttle of chipignite so I am in bit of a rush.

@naina singhal Without running any simulations to verify and just based on my limited understanding, please ensure that

vddio

is greater or equal to

vdda1

,

vdda2

,

vdda

and any connections to

gpio_analog

or

gpio_noesd

.

Ok. Thank you so much @Mitch Bailey 🙂

It doesn’t hurt to tie them all to ground if your gpio’s are configured for analog io.

Ok. I have connected all

io_out

and

io_oeb

of 27 gpio pads in caravan wrapper to

ground

. Moreover, I will set all the gpio pins to

GPIO_MODE_MGMT_STD_ANALOG

in

user_defines.v

, Thanks a lot @Mitch Bailey.