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<!channel>: Quickie challenge Per the discussion ...
# analog-design
t
<!channel>: Quickie challenge Per the discussion above (Friday, May 17) between Troy Benjegerdes, Bora Nikolic, and me: Putting my money where my mouth is, as the saying goes. I will personally offer one free TinyTapeout slot to the first person unrelated to Berkeley and BAG development who can install all the tools as described and produce and post GDS of a 12-bit ADC in Sky130 without involving a proprietary tool. Also needs to come with a writeup of all the steps from beginning to end. (Per comment below by Bora, instead of a 12-bit ADC, whatever is the maximum resolution supported by the repository will be considered sufficient.) The starting point is https://github.com/ucb-art/bag3_sync_sar_adc
👀 5
👍 9
👍🏼 1
😎 2
t
Will you accept a writeup in the form of the README for a debian package?
t
"Bonus points" to anybody who can do it in a Debian or Ubuntu environment (note that the first page of BAG3++ documentation specifically calls out CentOS/Red Hat packages). An ASCII text README file is perfectly fine for documentation.
a
Does nvidia proprietary driver count as proprietary?
t
Sounds like a "gray area" to me. Is there something that is specifically reliant on an nvidia driver?
t
I think this effort needs a channel all it's own
t
There is a #bag channel; seems appropriate.
t
I created #debian as a placeholder. I am certainly not going to use any Nvidia binary blobs...
Based on what it took me to get Firesim into a commercially usable state I'd say this is a 2-4 month project...
since it seems like they inherited at least something from Chipsalliance..
o
Did I miss something? According to the docs you need Virtuoso
t
@Or Dicker: I am still a bit unclear on that point, but a re-reading of the text made me think that Virtuoso is only required for the preparation of the PDK for use with BAG3++, and not for just using BAG3++ to build out a design. Still, the fact that Virtuoso is required for the preparation of the PDK is the kind of chink in the armor that Cadence lawyers would take a crowbar to.
b
Tagging @Bob Zhou @Felicia Guo. Keep in mind that 12b is outside the current generator’s range. Cadence approved the BAG kit
o
I looked at BAG3++. It seems like the setup_script.sh would fail. https://github.com/ucb-art/bag3_skywater130_workspace/blob/a9e174ab9fada81d3b4c06b466116bd3f898b21c/setup_script.sh#L96 Can I just comment it out? Doesn’t look like it would work
t
@Or Dicker try this and tell me if it works, or what fails next.. https://github.com/tmagik/bag3_skywater130_workspace/blob/master/setup_script.sh
y
I worked within a mosaic team to make a proof of concept with bag where we took out the virtuoso parts and plugged in xschem and KLayout. It's not fully completed but should be a good start for anyone working on this. https://gitlab.com/mosaic_group/mosaic_BAG/opensource_db_template
f
Hi all, just a couple of comments: 1. The ADC was tested for up to 8 bits with Cadence tools 2. You'll find initial setup for BAG dependencies here: https://bag3-readthedocs.readthedocs.io/en/latest/dependencies/ 3. Please note that the 
.bashrc
straight out of the workspace clone will not work for your environment. Paths must be updated for your specific machine/server per https://bag3-readthedocs.readthedocs.io/en/latest/workspaces/ . 4. BAG3++ is capable of generating a GDS without the use of virtuoso, as well as a 
.cdl
netlist. For example, for a 
bag3_digital
inverter that comes with the BAG Skywater workspace, one can run: 
./gen_cell.sh data/bag3_digital/specs_blk/inv_chain/gen.yaml -raw -netlist
. The 
.cdl
and the 
.gds
will show up in the respective folder pointed to in the 
root_dir
field of the yaml file. We do not currently have a Berkeley-supported open source schematic interface.
t
@Felicia Guo I have the pybag dependencies working on Ubuntu 22, but since there are no unit tests, I have no way to test it. Can you let us know who might have the tests, and what we could do to add them to the public version?
f
We usually just try to generate an inverter and check that the resulting design is LVS + DRC clean. Unit tests are a nice to have, that we also do not currently have. The main pybag library was written by a few students who have already graduated, and I am also not aware of them having ever made any shared unit tests, even among students.
t
@Felicia Guo can you let me know some professors at Berkeley who might be interested in finding some CS or Computer engineering students to write unit tests for cbag (the c++ part) ? Or let me know who's leading the current research effort
f
@Borivoje Nikolic can probably comment best here
b
@Troy Benjegerdes Feel free to contact me with a pointer for funding students, and I can find them. Unit tests smaller than an inverter may be nice, @Bob Zhou may be able to point to some if we have them.
n
Managed to get 
pybag
compiled on Ubuntu (couldn't get HDF5 warning sorted out), when attempting to generate an inverter:
Copy code
WARNING: Error registering BLOSC filter for HDF5.  Default to LZF
creating BAG project
*WARNING* invalid literal for int() with base 10: ''.  Operating without Virtuoso.
computing layout...
[2024-05-29 16:50:09.996] [STDCellWrapper] [warning] ports on private layer 0 detected, converting to primitive ports.
[2024-05-29 16:50:09.997] [STDCellWrapper] [warning] ports on private layer 0 detected, converting to primitive ports.
[2024-05-29 16:50:09.997] [STDCellWrapper] [warning] ports on private layer 2 detected, converting to primitive ports.
[2024-05-29 16:50:09.997] [STDCellWrapper] [warning] ports on private layer 2 detected, converting to primitive ports.
computation done.
creating layout...
Traceback (most recent call last):
  File "BAG_framework/run_scripts/gen_cell.py", line 82, in <module>
    run_main(_prj, _args)
  File "BAG_framework/run_scripts/gen_cell.py", line 68, in run_main
    gen_netlist=args.gen_netlist)
  File "/home/nmendez/asic/bag3_skywater130_workspace/BAG_framework/src/bag/core.py", line 479, in generate_cell
    square_bracket=square_bracket)
  File "/home/nmendez/asic/bag3_skywater130_workspace/BAG_framework/src/bag/layout/template.py", line 153, in batch_layout
    self.batch_output(output, info_list, **kwargs)
  File "/home/nmendez/asic/bag3_skywater130_workspace/BAG_framework/src/bag/util/cache.py", line 720, in batch_output
    lay_map = get_gds_layer_map()
  File "/home/nmendez/asic/bag3_skywater130_workspace/BAG_framework/src/bag/env.py", line 223, in get_gds_layer_map
    raise ValueError(f'{ans} is not a file.')
ValueError: /home/nmendez/asic/bag3_skywater130_workspace/skywater130/gds_setup/gds.layermap is not a file.

> /home/nmendez/asic/bag3_skywater130_workspace/BAG_framework/src/bag/env.py(223)get_gds_layer_map()
-> raise ValueError(f'{ans} is not a file.')
(Pdb)
gds.layermap is a symbolic link, which points to 
../workspace_setup/PDK/VirtuosoOA/libs/s8phirs_10r/s8phirs_10r.layermap
f
Can you try pulling the 
open
branch of the 
skywater130
submodule in the bag workspace? I just adapted the open source layermap into a gds.layermap file.
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n
@Felicia Guo It works, thank you! I'll check DRC, and then will try with the ADC generator.
Hi @Tim Edwards, I don't know if the challenge it's still up, this is what I could get: https://github.com/nmendezst/bag3_adc_test/ There is a 
gds
generated of the top level 8-bit ADC according to this inventory. Couldn't check DRC yet (I don't know if it's the same rule deck), got my setup mixed up with 
volare
and 
open_pdks
, I'll try later.
t
Any idea if the generated ADC will fit in a single tinytapeout slot?
t
@Norman Méndez: Yes, the challenge is still up, and congratulations! I owe you a TinyTapeout slot. : ) @Troy Benjegerdes: I don't know the size of a TinyTapeout slot, but at an area of 400um x 570um, I assume not. It is not a compact layout. I would have to extract and run a simulation to verify the function, but at a top-level view, it looks fine. It has a 10 bit output. One interesting thing about this system is that it generates its own digital standard cells, then places and routes them. There are a large number of DRC errors related to tap distance (latch-up rules); they all look easy enough to resolve manually. There is an error with cap bottom plate spacing which I think is a real error but I think this is an issue with the PDK, since we're still trying to find out from SkyWater ourselves how that rule is actually implemented. Assuming it really is an error, solving it would cause the capacitor array to get a bit wider, but nothing major. I am not sure what it's doing with ports, as it appears to have made an excessive number of ports (77) that includes a lot of internal signals. If I can figure out how to hook it up, I will put it on silicon. It only runs at 1.8V and has a differential input, so it doesn't meet my requirements of the moment, but on the other hand, the other two ADC designs that I know of (Christoph Weiser's and Manuel Moser's) are also both 1.8V and differential input, so all three can be directly compared.
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b
Congratulations, @Norman Méndez !
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@Tim Edwards feel free to PR any fixes. We have fabricated an 8-bit version of it, and it reaches somewhere around 50dB of SNR and 15MHz of BW (in what we believe is an SF corner; it may get a bit better in TT). Less bits will make it smaller. To get the best performance, make sure to have a solid grid above the sampler. You can look at how it is hooked up in out June'23 run, but improve the supply grid please. Keep in mind that the layout of the ADC itself is pretty compact, but the logic can be further compacted. The layout aspect ratio makes it amenable to interleaving, if you were puzzled about it. The idea of putting this design out there is to get people to use it, but also to improve it.
f
Adding a couple of usage comments + specific fixes done to the June '23 tapeout. Re DRCs: I manually fixed latch up rules for our tapeout, though this could also be done in the BAG generator. We waived the MIM cap issues. There seems to be some difference between the open source DRC check and the Cadence one we have used, so the Cadence DRC checks do not have this MIM cap issue. Just fyi the other manual fix/virtual connect needed is for the `CLK16`and `CLK16_B`nets to be connected between the samplers and the divided clock. This is doable in BAG, but I need to find the time to circle back and fix that, so if others are interested in looking into these problems + PR fixes please feel free. Re Testing: There are a lot of internal ports exposed for the purposes of debugging extracted simulation, however these are the ones that actually require a connection to an outside input/output if integrating are:
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DATA_OUT<9:1>
VDD VSS CLK IN_N IN_P VREF<2> VREF<1> VREF<0>
When I tested the bits I only used 
DATA_OUT<9:1>
- so 9 bits of output to make 8 bits of resolution. The last bit is an artifact from when this ADC was originally asynchronous, so should not be used. The capacitors are weighted for redundancy, so from largest to smallest the weights were 
[112, 64, 36, 20, 12, 6, 3, 2, 1]
. Also the input clock must be 11x your desired sample rate (ex put 176MHz into CLK if you want 16MHz sample frequency, the system is synchronous). 
VREF<2:0>
correspond to higher DC bias level, common-mode level, and lower DC bias level respectively for a differential ADC setup.
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t
@Borivoje Nikolic: I have to survive the June 3 shuttle run first, then I will look at making pull requests back to the BAG3++ repository.
o
Hi I got stuck at bag3_skywater130_workspace installation (./run_test.sh)
Does someone got the same problem?>
t
@Or Dicker: Did you look through the list of code changes that @Norman Méndez did in https://github.com/nmendezst/bag3_adc_test/? He did encounter an issue with C++ package 
std::optional
, although it was not the same error as shown in your screenshot. See the README file in Norman's repository, section 8 "Building cbag and pybag".
o
Thanks! I guess nmendezst finished the challenge?
m
should we extend the competition to include getting it DRC clean and ready to actually submit?
t
@Matt Venn: It would have to be a new competition---I already sent Norman a TinyTapeout voucher. But it seems like a great challenge: Get a validated BAG-generated layout onto TinyTapeout.
m
OK, let's consider this competition open. The first person to tapeout a BAG generated layout on TT will win a free analog slot. Once you have your design ready to go with green CI status lights, DM me.
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