Mm, my bad on that last graph: had a dumb short with my resistor connections and li, now the graphs are more sensible. Other bulletpoint questions stand, tho: is this a sensible investigation with these tools?

The extracted values should be more or less correct, and should fairly accurately represent both inter-layer parasitics and parasitics to substrate. Generally, for simple metal strips over shield planes, it's easier just to look at the output netlist and see what the parasitic value is.

Yes, I'm playing with tracks and the parax spice is simple, but was just warming up 🙂 m1/m2 come out the same stated R, m3/m4 form a pair as well, and the cap goes down as we go up (although only a couple of fF even for really fat tracks). This is great, thanks! Oh, speaking of metal layers, there was some discussion on the Z2A discord quoting you, stating a calculated 0.65mA/um for m1 wires but comparing that to the

DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC

found in _sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef_ for met1. If no ones pinged you on that, I could be the carrier pigeon for any clarifs.

Is this something we can test on tinytapeout, or or would we need to have bare pads or bare die to really confirm that simulation matches actual? Also how do process corners work for this kind of thing?

I'd say the answer is, yeah, you can test this through TT but it feels like the instrumentation would have to be on-chip--what I mean is that I'm looking at capacitances in the 10fF range, here, at best. The analog pins to get out of there: quoted at <5 pF... thus we'd have to do something internally, say an oscillator or whatever, that is sensitive enough to what we're measuring and outputs something we can exfiltrate through all the muxing without loss. As for process corners: others would be better equipped to answer on that front than I, that's fer sure.

Pat, Basic extraction model methods should be absolutely good enough to show resistance and capacitance effects 1st order to sidewall and layer to layer. No inductances are modelled. You are good to use this method Cap only up to about 2Ghz operations on wire lengths up to about 1mm. Scale F down linearly for L going up. 1st issue I think you might find is that tempco of wire resistance is not modelled..(Actually quite significant for a long wires with a high capacitive load).