Looking at the device details (

sky130_fd_pr__pfet_g5v0d10v5

specifically here, but all FET have equivalent) in the read the docs site, they say the spice model is only valid for

Vgs = 0 ... -5.5V

Does that mean the gate can never be higher than the source ? I was looking at voltage conversion from 3.3v signal down to 1.8v core and AFAICT people were just doing an inverter using the 3v3/5v devices and "powering" then from 1.8v core rail. But that means the gate of the pmos would end up above the source if the input is 3.3V .

Huh, wouldn't that circuit apply 3.3v on MN4 which if I read it correctly would be a 1.8v device (thin oxide) ?

Yep. It's dangerous. MN4 should be replaced with a thick oxide device. The conventional high to low is not a problem. Vgs can be negative for the PMOS. The real problem is rise and fall times for high speed signals.

For my application, speed is really not a concern 😅 But good to know Vgs can be negative.

It's a latch. This, for sure, won't cause any PMOS transistors to have positive vgs. It shouldn't be a problem, because varactors are made this way when they operate in accumulation. The most important thing is that the voltage drop in the oxide is not greater than the specified by the technology.